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参数资料
| 型号： | EM6640SO18A |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 8-SOIC |
| 中文描述： | 微控制器 |
| 文件页数： | 18/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18A |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
25
www.emmicroelectronic.com
7.2 Frequency Select and Up/Down Counting
8 different input clocks can be selected to drive the Counter. The selection is done with bits CountFSel2…0 in
register RegCCntl1. 6 of this input clocks are coming from the prescaler. The maximum prescaler clock
frequency for the counter is half the system clock and the lowest is 1Hz. Therefore a complete counter roll over
can take as much as 17.07min (1Hz clock, 10 bit length) or as little as 53.3
s (ck[19], 4 bit length). The
IRQCount0, generated at each roll over, can be used for time bases, measurements length definitions, input
polling, wake up from Halt Mode, etc. The IRQCount0 and IRQComp are generated with the system clock
(ck[20]) rising edge. IRQCount0 condition in UpCount Mode is : reaching 3FF if 10-bit counter length (resp FF, 3F,
F in 8, 6, 4-bit counter length). In DownCount Mode the condition is reaching ‘0’. The nonselected bits are ‘don’t
care’. For IRQComp refer to section 7.4.
Note:
The Prescaler
and the Microprocessor clock’s are usually non-synchronous, therefore timebases
generated are max n, min n-1 clock cycles long (n being the selected counter start value in count down mode).
However the prescaler clock can be synchronized with the
P commands using the prescaler reset function.
The two remaining clock sources are coming from the PA[0] or PA[3] terminals. Refer to chapter PortA on page
16 for details. Both sources can be either debounced (ck[17], ck[8]) or direct inputs, the input polarity can also be
chosen. The output after the debouncer polarity selector is named PA3 , PA0 resp. For the debouncer and input
In the case of PortA input clock without debouncer, the counting clock frequency will be half the input clock on
PortA. The counter advances on every odd numbered PortA negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA3 or PA0 input clock edge. In this condition the
EM6640 is able to count with a higher clock rate as its internal system clock (Hi-Frequency Input).
(Maximum PortA input frequency is at least 1MHz (@VDD
≥ 1.9V)).
In both, up or down count mode, the counter is cyclic. The counting direction is chosen in register RegCCntl1 bit
Up/Down (default=0, down counting). The counter increases or decreases its value with each positive clock edge
of the selected input clock source. Start up synchronization is necessary because one can not always know the
clock status when enabling the counter. With EvCount=0, the counter will only start on the next positive clock
edge after a previously latched negative edge, while the Start bit was already set to ‘1’.
This synchronization is done differently if Event Count Mode (bit EvCount) is chosen. Refer also to Figure 19.
Figure 18. Counter Clock Timing
pre s c a le r freq . or de boun ce d P o rtA c loc ks
N o n d ebou nc ed P o rtA c loc k s (s ys te m c loc k indep ende nt)
system c loc k
p re sca le r clo c k
co untin g
co unter IR Q ’s
div ided c loc k
system c loc k
Po rtA c lo c k
co untin g
c ounter IR Q ’s
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相关代理商/技术参数 |
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| EM6640SO18B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| EM6640TP16A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
| EM6640TP16B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microcontroller |
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