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| 型号： | EM6640SO18A |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 8-SOIC |
| 中文描述： | 微控制器 |
| 文件页数： | 3/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18A |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
11
www.emmicroelectronic.com
4.5 Digital Watchdog Timer Reset
The Digital Watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of CK[1]. It will
generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by activating
an inhibit digital watchdog bit (NoLogicWD) located in RegSysCtl3. By metal 1 mask option, one can force the
Digital Watchdog to be always active, this mean that the bit NoLogicWD has no more effect (see: Digital
Watchdog Option, page 50). In that case, the read of the bit NoLogicWD will always give ‘0’. By default, the
Digital Watchdog can be controlled by the register RegSysCtl3. At power up, and after any System Reset, the
watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the System Reset
signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the
watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 600kHz), or a
System Reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and timer
operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer operates
also in the STANDBY mode and thus, to avoid a System Reset, STANDBY should not be active for more than 2.5
seconds.
From a System Reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog
timer is reset at any other time, then it could become active after just 2.5 seconds. In addition, using the
Prescaler reset function can lower this minimum watchdog time. It is therefore recommended to use the Prescaler
IRQ1Hz interrupt to periodically reset the watchdog every one second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the counting
sequence is (on each rising edge of CK[1]) : {WDVal1 WDVal0} ‘00’, ‘01’, ‘10’, ‘11’. When in the ‘11’ state, the
watchdog reset will be active within second. The watchdog reset activates the system reset which in turn
resets the watchdog. If the watchdog is inhibited its timer is reset and therefore always reads ‘0’.
Table 4.5.1 Watchdog timer register RegSysCntl2
Bit
Name
Reset
R/W
Description
3
WDReset
0
R/W
Reset the Watchdog
1 -> Resets the Logic Watchdog
0 -> no action
The Read value is always '0'
2
SleepEn
0
R/W
see Operating modes (sleep)
1
WDVal1
0
R
Watchdog timer data 1/4 ck[1]
0
WDVal0
0
R
Watchdog timer data 1/2 ck[1]
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