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| 型号： | EM6640SO18A |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 8-SOIC |
| 中文描述： | 微控制器 |
| 文件页数： | 32/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18A |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
38
www.emmicroelectronic.com
10. Interrupt Controller
The EM6640 has 12 different interrupt request sources individually maskable. These are :
External(4)
- PortA(4)
PA[3] .. PA[0] inputs
Internal(8)
- Prescaler(3)
9.4kHz, 586Hz, 1Hz
- 10-bit Counter(2)
Count0, CountComp
-SWB(1)
SWBuff empty in interactive mode
-SVLD(1)
End of measure
-EEPROM(1)
End of writing operation
To be able to send an interrupt to the CPU, at least one of the interrupt request flags must be set (IRQxx) and the
general interrupt enable bit IntEn located in the register RegSysCntl1 must be set to 1. The interrupt request
flags can only be set by a positive edge of IRQxx with the corresponding mask register bit (MaskIRQxx) set to 1.
Figure 26. Interrupt Controller Block Diagram
At power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any
interrupt request to be stored. Also the general interrupt enable IntEn is set to 0 (No IRQ to CPU) by reset.
After each read operation on the interrupt request registers RegIRQ1, RegIRQ2 or RegIRQ3 the contents of the
addressed register are reset. Therefore one has to make a copy of the interrupt request register if there was more
than one interrupt to treat. Each interrupt request flag may also be reset individually by writing 1 into it (ClrIntBit).
Interrupt handling priority must be resolved through software by deciding which register and which flag inside the
register need to be serviced first.
Since the CPU has only one interrupt subroutine and because the IRQxx registers are cleared after reading, the
CPU does not miss any interrupt request which come during the interrupt service routine. If any occurs during this
time a new interrupt will be generated as soon as the software comes out of the current interrupt subroutine.
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their
corresponding mask setting and not on the general interrupt enable status.
Whenever the EM6640 goes into HALT Mode the IntEn bit is automatically set to 1, thus allowing to resume from
Halt Mode with an interrupt.
DB
Write
IRQ
Read
ClrIntBit
Reset
One of these blocks for each IRQ input
12 In-OR
Interrupt request
capture register
Mask
DB
Writ
Halt
AutoSWB
INT to
P
SET
General
INT En
SWBempty
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| EM6640WP11 | 制造商:EMMICRO 制造商全称:EM Microelectronic - MARIN SA 功能描述:Low Power Microcontroller with EEPROM AND RC Oscillator |
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