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| 型号： | EM6640SO18A |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 8-SOIC |
| 中文描述： | 微控制器 |
| 文件页数： | 24/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18A |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
30
www.emmicroelectronic.com
8. Serial (Output) Write Buffer - SWB
The EM6640 has Serial Write Buffer which outputs serial data and serial clock coming from prescaler or a other
mode where the clock can be fed from outside (PA[0]).
The SWB is enabled by setting EnSWB bit in RegSWBCntl and by setting the PortC in output mode.
Serial Write Buffer clock is selected by the SWBFSel0 and SWBFSel1 bits in the RegSWBCntl register.
TestVar[3] signal, which is used to make conditional jumps, indicates "Transmission finished" in automatic send
mode or "SWBbuffer empty " interrupt in interactive send mode. In interactive mode, TestVar[3] is equivalent to
the interrupt request flags stored in RegIRQi registers : it permits to recognize the interrupt source. (See also the
interrupt handling section 10 for further information). To serve the "SWBbuffer empty " interrupt request, one only
has to make a conditional jump on TestVar[3].
On the receiver side, serial data can be evaluated on serial clock falling edge. Internally, new data goes out on
rising edge of the same clock.
By default the SWBdata level (on PPC[1]) will be equal to VDD as are all the others terminals. Depending on the
metal1 option MSWBdataLevel (refer to SWBdataLevel Option, on page 50), the level of PPC[1] can be selected
as VregLogic. When this metal option is in place, VregLogic is increased by
50mV.
In this case, a high current can be drawn from this terminal without penalizing the output level (see DC
characteristics on page 57).
This allows to transmit the data through a RF module for instance, without an additional regulator or amplifier.
To guarantee the electrical characteristics when PPC[1] is selected as VregLogic, VDD should not be below 2.2v
to output 2mA. If the PPC[1] terminal is used as an input, it’s input high level has to be VregLogic.
Size[5:0]
Addr. Counter
RAM
80 nibbles
SWB buffer
SWBauto
SWBStart
SWBFSel0,1
Control
Logic
Shift register
Clk
Mux
SWB clock
SWB data
TestVar3
SWB buffer
register empty
IRQ (only in
interactive mode)
d
a
t
a
b
u
s
PA[0]/9.4kHz
2.3kHz
150kHz
75kHz
EnSWB
1
0
PC[1]
PC[0]
Figure 22 Serial write buffer
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