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参数资料
| 型号： | EP20K100BI324-3 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA324 |
| 文件页数： | 31/68页 |
| 文件大小： | 975K |
| 代理商： | EP20K100BI324-3 |
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37
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Figure 7-5.
PCK Clocking System AT90PWM2B/3B
7.6.2
PLL Control and Status Register – PLLCSR
Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM2/2B/3/3B and always read as zero.
Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64Mhz.
If PLLF is clear, the PLL output is 32Mhz.
Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this bit
is always 1.
Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLKPLL for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
7.7
128 kHz Internal Oscillator
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25
C. This clock is used by the Watchdog Oscillator.
7.8
External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure
7-6. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
8 MHz
RC OSCILLATOR
OSCCAL
XTAL1
XTAL2
OSCILLATORS
DIVIDE
BY 8
DIVIDE
BY 2
CK
PLL
64x
PLLE
Lock
Detector
PLOCK
SOURCE
PLLF
DIVIDE
BY 4
CLK
PLL
CKSEL3..0
Bit
7
6543
210
$29 ($29)
–
––––
PLLF
PLLE
PLOCK
PLLCSR
Read/Write
RR
RRR
R/W
R
Initial Value
0
0000
0
0/1
0
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| EP20K100BI356-1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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| EP20K100BI356-3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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