参数资料
| 型号： | EP20K300EQC240-3 |
| 厂商： | Altera |
| 文件页数： | 107/117页 |
| 文件大小： | 0K |
| 描述： | IC APEX 20KE FPGA 300K 240-PQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 24 |
| 系列： | APEX-20K® |
| LAB/CLB数： | 1152 |
| 逻辑元件/单元数： | 11520 |
| RAM 位总计： | 147456 |
| 输入/输出数： | 152 |
| 门数： | 728000 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 240-BFQFP |
| 供应商设备封装： | 240-PQFP（32x32） |
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Altera Corporation
9
APEX 20K Programmable Logic Device Family Data Sheet
Functional
Description
APEX 20K devices incorporate LUT-based logic, product-term-based
logic, and memory into one device. Signal interconnections within
APEX 20K devices (as well as to and from device pins) are provided by the
FastTrack Interconnect—a series of fast, continuous row and column
channels that run the entire length and width of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer and a register that can be used as either an input
or output register to feed input, output, or bidirectional signals. When
used with a dedicated clock pin, these registers provide exceptional
performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,
66-MHz PCI compliance; JTAG BST support; slew-rate control; and
tri-state buffers. APEX 20KE devices offer enhanced I/O support,
including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,
3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V
AGP I/O standards.
The ESB can implement a variety of memory functions, including CAM,
RAM, dual-port RAM, ROM, and FIFO functions. Embedding the
memory directly into the die improves performance and reduces die area
compared to distributed-RAM implementations. Moreover, the
abundance of cascadable ESBs ensures that the APEX 20K device can
implement multiple wide memory blocks for high-density designs. The
ESB’s high speed ensures it can implement small memory blocks without
any speed penalty. The abundance of ESBs ensures that designers can
create as many different-sized memory blocks as the system requires.
Figure 1 shows an overview of the APEX 20K device.
Figure 1. APEX 20K Device Block Diagram
LUT
Memory
IOE
LUT
Memory
IOE
Product Term
LUT
Memory
IOE
Product Term
FastTrack
Interconnect
Clock Management Circuitry
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
standards.
ClockLock
Four-input LUT
for data path and
DSP functions.
Product-term
integration for
high-speed
control logic and
state machines.
Flexible integration
of embedded
memory, including
CAM, RAM,
ROM, FIFO, and
other memory
functions.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K300EQC240-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K300EQC240-3N | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1152 Macro 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K300EQI240-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K300EQI240-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K300EQI240-2X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1152 Macros 152 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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