收藏本站
参数资料
型号： EP20K300EQC240-3
厂商： Altera
文件页数： 80/117页
文件大小： 0K
描述： IC APEX 20KE FPGA 300K 240-PQFP
产品培训模块： Three Reasons to Use FPGA's in Industrial Designs
标准包装： 24
系列： APEX-20K®
LAB/CLB数： 1152
逻辑元件/单元数： 11520
RAM 位总计： 147456
输入/输出数： 152
门数： 728000
电源电压： 1.71 V ~ 1.89 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 240-BFQFP
供应商设备封装： 240-PQFP（32x32）
Altera Corporation
65
APEX 20K Programmable Logic Device Family Data Sheet
1
For DC Operating Specifications on APEX 20KE I/O standards,
please refer to Application Note 117 (Using Selectable I/O Standards
in Altera Devices).
Notes to Tables 27 through 30:
(1)
See the Operating Requirements for Altera Devices Data Sheet.
(2)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to the voltage
shown in the following table based on input duty cycle for input currents less than 100 mA. The overshoot is
dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle.
Vin
Max. Duty Cycle
4.0V
100% (DC)
4.1
90%
4.2
50%
4.3
30%
4.4
17%
4.5
10%
(6)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(7)
Typical values are for TA = 25° C, VCCINT = 1.8 V, and VCCIO = 1.8 V, 2.5 V or 3.3 V.
(8)
These values are specified under the APEX 20KE device recommended operating conditions, shown in Table 24 on
page 60.
(9)
Refer to Application Note 117 (Using Selectable I/O Standards in Altera Devices) for the VIH, VIL, VOH, VOL, and II
parameters when VCCIO = 1.8 V.
(10) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
(11) The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(12) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(13) This value is specified for normal device operation. The value may vary during power-up.
(14) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
(15) Capacitance is sample-tested only.
Figure 33 shows the relationship between VCCIO and VCCINT for 3.3-V PCI
compliance on APEX 20K devices.
Table 30. APEX 20KE Device Capacitance
Note (15)
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on
dedicated clock pin
VIN = 0 V, f = 1.0 MHz
12
pF
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
相关PDF资料
PDF描述
EP4CGX110CF23C7 IC CYCLONE IV FPGA 110K 484FBGA
AX500-2FGG676I IC FPGA AXCELERATOR 500K 676FBGA
AX500-2FG676I IC FPGA AXCELERATOR 500K 676FBGA
A54SX32-1BG329I IC FPGA SX 48K GATES 329-BGA
A54SX32-2BGG329 IC FPGA SX 48K GATES 329-BGA
相关代理商/技术参数
参数描述
EP20K300EQC240-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K300EQC240-3N 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1152 Macro 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K300EQI240-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K300EQI240-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K300EQI240-2X 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1152 Macros 152 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*