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参数资料
型号： EP20K300EQC240-3
厂商： Altera
文件页数： 77/117页
文件大小： 0K
描述： IC APEX 20KE FPGA 300K 240-PQFP
产品培训模块： Three Reasons to Use FPGA's in Industrial Designs
标准包装： 24
系列： APEX-20K®
LAB/CLB数： 1152
逻辑元件/单元数： 11520
RAM 位总计： 147456
输入/输出数： 152
门数： 728000
电源电压： 1.71 V ~ 1.89 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 240-BFQFP
供应商设备封装： 240-PQFP（32x32）
62
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Notes to Tables 23 through 26:
(1)
See the Operating Requirements for Altera Devices Data Sheet.
(2)
All APEX 20K devices are 5.0-V tolerant.
(3)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
(4)
Numbers in parentheses are for industrial-temperature-range devices.
(5)
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(6)
All pins, including dedicated inputs, clock I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(7)
Typical values are for TA= 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 or 3.3 V.
(8)
These values are specified in the APEX 20K device recommended operating conditions, shown in Table 26 on
page 62.
(9)
The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the
input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 33 on page 68.
(10) The IOH parameter refers to high-level TTL, PCI or CMOS output current.
(11) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(12) This value is specified for normal device operation. The value may vary during power-up.
(13) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
(14) Capacitance is sample-tested only.
Tables 27 through 30 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for 1.8-V APEX 20KE devices.
Table 26. APEX 20K 5.0-V Tolerant Device Capacitance
Notes (2), (14)
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on dedicated
clock pin
VIN = 0 V, f = 1.0 MHz
12
pF
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
Table 27. APEX 20KE Device Absolute Maximum Ratings
Note (1)
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT Supply voltage
With respect to ground (2)
–0.5
2.5
V
VCCIO
–0.5
4.6
V
VI
DC input voltage
–0.5
4.6
V
IOUT
DC output current, per pin
–25
25
mA
TSTG
Storage temperature
No bias
–65
150
° C
TAMB
Ambient temperature
Under bias
–65
135
° C
TJ
Junction temperature
PQFP, RQFP, TQFP, and BGA packages,
under bias
135
° C
Ceramic PGA packages, under bias
150
° C
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相关代理商/技术参数
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EP20K300EQC240-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K300EQC240-3N 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1152 Macro 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K300EQI240-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K300EQI240-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K300EQI240-2X 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 1152 Macros 152 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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