EP20K30EQC208-1 (Altera) PDF资料下载 Datasheet(34/117 页)

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Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Figure 11 shows the intersection of a row and column interconnect, and

how these forms of interconnects and LEs drive each other.

Figure 11. Driving the FastTrack Interconnect

APEX 20KE devices include an enhanced interconnect structure for faster

routing of input signals with high fan-out. Column I/O pins can drive the

FastRow interconnect, which routes signals directly into the local

interconnect without having to drive through the MegaLAB interconnect.

FastRow lines traverse two MegaLAB structures. Also, these pins can

drive the local interconnect directly for fast setup times. On EP20K300E

and larger devices, the FastRow interconnect drives the two MegaLABs in

the top left corner, the two MegaLABs in the top right corner, the two

MegaLABS in the bottom left corner, and the two MegaLABs in the

bottom right corner. On EP20K200E and smaller devices, FastRow

interconnect drives the two MegaLABs on the top and the two MegaLABs

on the bottom of the device. On all devices, the FastRow interconnect

drives all local interconnect in the appropriate MegaLABs except the local

interconnect on the side of the MegaLAB opposite the ESB. Pins using the

FastRow interconnect achieve a faster set-up time, as the signal does not

need to use a MegaLAB interconnect line to reach the destination LE.

Figure 12 shows the FastRow interconnect.

Row Interconnect

MegaLAB Interconnect

Column

Interconnect

Local

Interconnect

相关代理商/技术参数	参数描述
EP20K30EQC208-1ES	制造商:未知厂家制造商全称:未知厂家功能描述:FPGA
EP20K30EQC208-2	制造商:Rochester Electronics LLC 功能描述:- Bulk
EP20K30EQC208-2ES	制造商:未知厂家制造商全称:未知厂家功能描述:FPGA
EP20K30EQC208-3	制造商:Rochester Electronics LLC 功能描述:- Bulk
EP20K30EQC208-3ES	制造商:未知厂家制造商全称:未知厂家功能描述:FPGA

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