参数资料
型号: EP20K30EQC208-1
厂商: Altera
文件页数: 55/117页
文件大小: 0K
描述: IC APEX 20KE FPGA 300K 208-PQFP
标准包装: 24
系列: APEX-20K®
LAB/CLB数: 120
逻辑元件/单元数: 1200
RAM 位总计: 24576
输入/输出数: 125
门数: 113000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
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参数描述
EP20K30EQC208-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K30EQC208-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP20K30EQC208-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K30EQC208-3 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP20K30EQC208-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA