参数资料
| 型号： | EP4S100G5F45I1 |
| 厂商： | Altera |
| 文件页数： | 20/22页 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 530K 1932FBGA |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB数： | 21248 |
| 逻辑元件/单元数： | 531200 |
| RAM 位总计： | 28033024 |
| 输入/输出数： | 781 |
| 电源电压： | 0.92 V ~ 0.98 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 1932-BBGA |
| 供应商设备封装： | 1932-FBGA（45x45） |
Chapter 1: Overview for the Stratix IV Device Family
1–7
Architecture Features
September 2012
Altera Corporation
■
XAUI/HiGig Support
■
Compliant to IEEE802.3ae specification
■
Embedded state machine circuitry to convert XGMII idle code groups (||I||)
to and from idle ordered sets (||A||, ||K||, ||R||) at the transmitter and
receiver, respectively
■
8B/10B encoder and decoder, receiver synchronization state machine, lane
deskew, and ± 100 ppm clock compensation circuitry
■
GbE Support
■
Compliant to IEEE802.3-2005 specification
■
Automatic idle ordered set (/I1/, /I2/) generation at the transmitter,
depending on the current running disparity
■
8B/10B encoder and decoder, receiver synchronization state machine, and
± 100 ppm clock compensation circuitry
■
Support for other protocol features such as MSB-to-LSB transmission in
SONET/SDH configuration and spread-spectrum clocking in PCIe configurations
Diagnostic Features
■
Serial loopback from the transmitter serializer to the receiver CDR for transceiver
PCS and PMA diagnostics
■
Reverse serial loopback pre- and post-CDR to transmitter buffer for physical link
diagnostics
■
Loopback master and slave capability in PCI Express hard IP blocks
f For more information, refer to the PCI Express Compiler User Guide.
Signal Integrity
Stratix IV devices simplify the challenge of signal integrity through a number of chip,
package, and board-level enhancements to enable efficient high-speed data transfer
into and out of the device. These enhancements include:
■
Programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis
levels to compensate for pre-cursor and post-cursor inter-symbol interference (ISI)
■
Up to 900% boost capability on the first pre-emphasis post-tap
■
User-controlled and adaptive 4-stage receiver equalization with up to 16 dB of
high-frequency gain
■
On-die power supply regulators for transmitter and receiver phase-locked loop
(PLL) charge pump and voltage controlled oscillator (VCO) for superior noise
immunity
■
On-package and on-chip power supply decoupling to satisfy transient current
requirements at higher frequencies, thereby reducing the need for on-board
decoupling capacitors
■
Calibration circuitry for transmitter and receiver on-chip termination (OCT)
resistors
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP4S100G5F45I1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4S100G5F45I1NGA | 制造商:Altera Corporation 功能描述: |
| EP4S100G5F45I2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4S100G5F45I2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP4S100G5F45I3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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