参数资料
| 型号： | EPC16UC88AA |
| 厂商： | Altera |
| 文件页数： | 36/36页 |
| 文件大小： | 0K |
| 描述： | IC CONFIG DEVICE 16MBIT 88-UBGA |
| 标准包装： | 80 |
| 系列： | EPC |
| 可编程类型： | 系统内可编程 |
| 存储容量： | 16Mb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 88-LFBGA |
| 供应商设备封装： | 88-UBGA（11x8） |
| 包装： | 托盘 |
| 其它名称： | 544-1373 EPC16UC88AA-ND |
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Functional Description
Page 9
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Finally, the configuration controller also manages errors during configuration. A
CONF
_DONE error occurs when the FPGA does not de-assert its CONF_DONE signal within
64 DCLK cycles after the last bit of configuration data is transmitted. When a CONF_DONE
error is detected, the controller pulses the OE line low, which pulls the nSTATUS signal
low and triggers another configuration cycle.
A cyclic redundancy check (CRC) error occurs when the FPGA detects corruption in
the configuration data. This corruption could be a result of noise coupling on the
board such as poor signal integrity on the configuration signals. When this error is
signaled by the FPGA (by driving the nSTATUS signal low), the controller stops
configuration. If the Auto-Restart Configuration After Error option is enabled in the
FPGA, it releases its nSTATUS signal after a reset time-out period and the controller
attempts to reconfigure the FPGA.
After the FPGA configuration process is complete, the controller drives the DCLK pin
low and the DATA[] pins high. Additionally, the controller tri-states its internal
interface to the flash memory, enables the weak internal pull-ups on the flash address
and control lines, and enables bus-keep circuits on flash data lines.
The following sections describe the different configuration schemes supported by the
EPC device—FPP, PS, and concurrent configuration schemes.
f For more information, refer to the configuration chapter in the appropriate device
handbook.
Configuration Signals
Table 4 lists the configuration signal connections between the EPC device and Altera
FPGAs.
Table 4. Configuration Signals
EPC Device Pin
Altera FPGA Pin
Description
DATA[]
Configuration data transmitted from the EPC device to the
FPGA, which is latched on the rising edge of DCLK.
DCLK
EPC device generated clock used by the FPGA to latch
configuration data provided on the DATA[] pins.
nINIT_CONF,
which
nCONFIG
Open-drain output from the EPC device that is used to
start FPGA reconfiguration using the initiate configuration
(INIT_CONF) JTAG instruction. This connection is not
needed if the INIT_CONF JTAG instruction is not needed.
If nINIT_CONF is not connected to nCONFIG, nCONFIG
must be tied to VCC either directly or through a pull-up
resistor.
OE
nSTATUS
Open-drain bidirectional configuration status signal,
which is driven low by either the EPC device or FPGA
during POR and to signal an error during configuration.
Low pulse on OE resets the EPC device controller.
nCS
CONF_DONE
Configuration done output signal driven by the FPGA.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPC16UC88N | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPC16UI88AA | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPC16UI88N | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPC16XXX | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPC17 | 制造商:TDK 制造商全称:TDK Electronics 功能描述:Ferrite Cores For Power Supply and Signal Transformer EPC Cores |
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