参数资料
| 型号： | EPCS16SI16N |
| 厂商： | Altera |
| 文件页数： | 18/40页 |
| 文件大小： | 0K |
| 描述： | IC CONFIG DEVICE 16MBIT 16-SOIC |
| 产品变化通告： | Product Discontinuation 01/31/2008 |
| 标准包装： | 49 |
| 系列： | EPCS |
| 可编程类型： | 系统内可编程 |
| 存储容量： | 16Mb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
| 其它名称： | 544-1240-5 EPCS16SI16 |
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EPCS Device Memory Access
Page 25
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Write Bytes Operation
The write bytes operation code is b'0000 0010 and it lists the MSB first. This
operation allows bytes to be written to the memory. You must execute the write enable
operation before the write bytes operation to set the write enable latch bit in the status
register to 1.
The write bytes operation is implemented by driving the nCS signal low, followed by
the write bytes operation code, three address bytes, and at least one data byte on the
ASDI
pin. If the eight LSBs (A[7..0]) are not all 0, all sent data that goes beyond the
end of the current page is not written into the next page. Instead, this data is written at
the start address of the same page (from the address whose eight LSBs are all 0). You
must ensure the nCS signal is set low during the entire write bytes operation.
If more than 256 data bytes are shifted into the EPCS device with a write bytes
operation, the previously latched data is discarded and the last 256 bytes are written
to the page. However, if less than 256 data bytes are shifted into the EPCS device, they
are guaranteed to be written at the specified addresses and the other bytes of the same
page are not affected.
If your design requires writing more than 256 data bytes to the memory, more than
one page of memory is required. Send the write enable and write bytes operation
codes, followed by three new targeted address bytes and 256 data bytes, before a new
page is written.
The nCS signal must be driven high after the eighth bit of the last data byte has been
latched in. Otherwise, the device does not execute the write bytes operation. The write
enable latch bit in the status register is reset to 0 before the completion of each write
bytes operation. Therefore, the write enable operation must be carried out before the
next write bytes operation.
The device initiates a self-timed write cycle immediately after the nCS signal is driven
high. For more information about the self-timed write cycle time, refer to the tWB value
in Table 16 on page 29. You must account for this amount of delay before another page
of memory is written. Alternatively, you can check the write in progress bit in the
status register by executing the read status operation while the self-timed write cycle
is in progress. The write in progress bit is set to 1 during the self-timed write cycle and
0
when it is complete.
1 You must erase all the memory bytes of the EPCS devices to all 1 or 0xFF before you
implement the write bytes operation. You can erase all the memory bytes by executing
the erase sector operation in a sector or the erase bulk operation throughout the entire
memory.
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