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参数资料
型号： EPF10K100EQI208-1DX
英文描述： ASIC
中文描述： 专用集成电路
文件页数： 19/120页
文件大小： 1901K
代理商： EPF10K100EQI208-1DX
Altera Corporation
115
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
All pins that are not listed are user I/O pins.
(2)
All FineLine BGA packages support SameFrame pin migration to allow migration from one package to another. The
MAX+PLUS II software performs this function automatically when future migration is set.
(3)
This pin is a dedicated pin and is not available as a user I/O pin.
(4)
This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function.
(5)
This pin can be used as a user I/O pin after configuration.
(6)
This pin is tri-stated in user mode.
(7)
This pin drives the ClockLock and ClockBoost circuitry.
(8)
This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry
is locked to the incoming clock and generates an internal clock, LOCK is driven high. LOCK remains high if a periodic
clock stops clocking. The LOCK function is optional; if the LOCK output is not used, this pin is a user I/O pin.
(9)
This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power
and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the
rest of the device. If the ClockLock or ClockBoost circuitry is not used, this power or ground pin should be
connected to VCCINT or GND, respectively.
(10) When using the EPF10K100B device, connect this pin to VCCINT.
(11) When using the EPF10K100B device, connect this pin to GNDINT.
(12) The user I/O pin count includes dedicated input pins, dedicated clock pins, and all I/O pins.
Table 90 shows pin compatibility between different FLEX 10KE devices.
Notes:
(1)
All FineLine BGA packages support SameFrame pin migration to allow migration from one package to another. The
MAX+PLUS II software automatically avoids conflicting pins when future migration is set.
(2)
Devices in the same package are pin-compatible and have the same number of I/O pins.
(3)
Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When
planning device migration, use the I/O pins that are common to all devices. The MAX+PLUS II software
versions 9.1 and higher provide features to help use only the common pins.
(4)
This option will be supported with a 484-pin FineLine BGA package. By using SameFrame pin migration, all
FineLine BGA packages are pin-compatible. For example, a board can be designed to support 256-pin, 484-pin, and
672-pin FineLine BGA packages. The MAX+PLUS II software automatically avoids conflicting pins when future
migration is set.
Table 90. FLEX 10KE Device Pin Compatibility
Note (1)
Device
144-Pin
TQFP
208-Pin
PQFP
240-Pin
PQFP
RQFP
599-Pin
PGA
356-Pin
BGA
600-Pin
BGA
256-Pin
FineLine
BGA
484-Pin
FineLine
BGA
672-Pin
FineLine
BGA
EPF10K30E
(2)
(3)
(4)
EPF10K50E
(2)
(3)
(4)
EPF10K50S
(2)
(3)
(4)
EPF10K100B
(2)
(3)
EPF10K100E
(2)
(3)
(4)
EPF10K130E
(3)
EPF10K200E
(2)
(3)
EPF10K200S
(3)
(2)
(3)
相关PDF资料
PDF描述
EPF10K100EQI208-2 Field Programmable Gate Array (FPGA)
EPF10K100EQI208-2DX ASIC
EPF10K100EQI208-3DX ASIC
EPF10K130EBC600-1X Field Programmable Gate Array (FPGA)
EPF10K130EBC600-2 Field Programmable Gate Array (FPGA)
相关代理商/技术参数
参数描述
EPF10K100EQI208-2 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EPF10K100EQI208-2DX 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC
EPF10K100EQI208-3DX 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC
EPF10K100EQI240-1DX 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC
EPF10K100EQI240-2DX 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC
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