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| 型号： | EPF10K100EQI208-1DX |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 47/120页 |
| 文件大小： | 1901K |
| 代理商： | EPF10K100EQI208-1DX |
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32
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
On all FLEX 10KE devices (except EPF10K50E and EPF10K200E), the
input path from the I/O pad to the FastTrack Interconnect has a
programmable delay element that can be used to guarantee a zero hold
time. EPF10K50S and EPF10K200S devices support this feature.
Depending on the placement of the IOE relative to what it is driving, the
designer may choose to turn on the programmable delay to ensure a zero
hold time or turn it off to minimize setup time. This feature is used to
reduce setup time for complex pin-to-register paths (e.g., PCI designs).
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices and provides up to 12 peripheral control signals that
can be allocated as follows:
s
Up to eight output enable signals
s
Up to six clock enable signals
s
Up to two clock signals
s
Up to two clear signals
If more than six clock enable or eight output enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, a LE in a different row can drive a column interconnect, which
causes a row interconnect to drive the peripheral control signal. The chip-
wide reset signal resets all IOE registers, overriding any other control
signals.
When a dedicated clock pin drives IOE registers, it can be inverted for all
IOEs in the device. All IOEs must use the same sense of the clock. For
example, if any IOE uses the inverted clock, all IOEs must use the inverted
clock and no IOE can use the non-inverted clock. However, LEs can still
use the true or complement of the clock on a LAB-by-LAB basis.
The incoming signal may be inverted at the dedicated clock pin and will
drive all IOEs. For the true and complement of a clock to be used to drive
IOEs, drive it into both global clock pins. One global clock pin will supply
the true, and the other will supply the complement.
When the true and complement of a dedicated input drives IOE clocks,
two signals on the peripheral control bus are consumed, one for each
sense of the clock.
相关PDF资料 |
PDF描述 |
|---|---|
| EPF10K100EQI208-2 | Field Programmable Gate Array (FPGA) |
| EPF10K100EQI208-2DX | ASIC |
| EPF10K100EQI208-3DX | ASIC |
| EPF10K130EBC600-1X | Field Programmable Gate Array (FPGA) |
| EPF10K130EBC600-2 | Field Programmable Gate Array (FPGA) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K100EQI208-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EQI208-2DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EQI208-3DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EQI240-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EQI240-2DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
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