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| 型号： | EPF10K100EQI208-1DX |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 31/120页 |
| 文件大小： | 1901K |
| 代理商： | EPF10K100EQI208-1DX |
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18
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the output
of the LUT drives the output of the LE.
The LE has two outputs that drive the interconnect: one drives the local
interconnect and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The FLEX 10KE architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports
high-speed counters and adders and the cascade chain implements
wide-input functions with minimum delay. Carry and cascade chains
connect all LEs in a LAB as well as all LABs in the same row. Intensive use
of carry and cascade chains can reduce routing flexibility. Therefore, the
use of these chains should be limited to speed-critical portions of a design.
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
FLEX 10KE architecture to implement high-speed counters, adders, and
comparators of arbitrary width efficiently. Carry chain logic can be
created automatically by the MAX+PLUS II Compiler during design
processing, or manually by the designer during design entry.
Parameterized functions such as LPM and DesignWare functions
automatically take advantage of carry chains.
Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
alternate LABs in a row. A carry chain longer than one LAB skips either
from even-numbered LAB to even-numbered LAB, or from odd-
numbered LAB to odd-numbered LAB. For example, the last LE of the
first LAB in a row carries to the first LE of the third LAB in the row. The
carry chain does not cross the EAB at the middle of the row. For instance,
in the EPF10K50E device, the carry chain stops at the eighteenth LAB and
a new one begins at the nineteenth LAB.
相关PDF资料 |
PDF描述 |
|---|---|
| EPF10K100EQI208-2 | Field Programmable Gate Array (FPGA) |
| EPF10K100EQI208-2DX | ASIC |
| EPF10K100EQI208-3DX | ASIC |
| EPF10K130EBC600-1X | Field Programmable Gate Array (FPGA) |
| EPF10K130EBC600-2 | Field Programmable Gate Array (FPGA) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K100EQI208-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 624 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K100EQI208-2DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EQI208-3DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EQI240-1DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EPF10K100EQI240-2DX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
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