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参数资料
| 型号： | EPF10K40 |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10K嵌入式可编程逻辑系列） |
| 文件页数： | 3/10页 |
| 文件大小： | 230K |
| 代理商： | EPF10K40 |
Philips Semiconductors
Application note
AN116
Applications for the NE521/522/527/529
1988 Dec
3
STATE-OF-THE-ART
Comparator design has always been optimized for four basic
parameters. They are:
1. High Speed
2. Wide Input Voltage Range
3. Low Input Current
4. Good Resolution
Unfortunately, these four parameters are not compatible. For
instance, gain and input current can be improved by using thinner
diffusions for higher beta, but only at the expense of input voltage
range. Higher gain also means higher saturation for an increase in
delay time. So it becomes obvious that older comparators such as
the 710 were designed with the best compromises in mind using
standard processing.
One method of improving overall response adds gold doping to the
processing flow. The gold dopant causes a decrease in minority
carrier lifetime which aids the recombination process and shortens
the saturation recovery time. Unfortunately, the transistor beta is
adversely affected by gold, causing slightly higher bias and offset
currents.
SL00730
Figure 4. Schottky Clamped Transistor
It was not until the advent of the Schottky clamp that a vast
improvement in speed without input degradation was possible. A
very familiar term in the semiconductor industry, the Schottky barrier
diode’s (SBD) location is illustrated in Figure 4.
The Schottky clamped transistor is formed by paralleling the
Schottky diode with the base-collector junction of the NPN transistor.
Without the clamp, as base drive is increased the collector voltage
falls until hard saturation occurs. At this point the collector voltage is
very near the emitter voltage, and stored charges in the junctions
causes slow recovery from saturation after base drive has been
removed. The forward voltage drop of the Schottky diode is
0.4V—less than the forward drop of silicon diodes. This difference in
forward drop is used by placing the diode across the transistor
base-collector junction.
The Schottky diode becomes forward-biased when the collector
voltage falls 0.4V below the base voltage. Excess base drive is then
shunted into the collector circuit, prohibiting the transistor from
reaching classic saturation. With almost no stored charge in either
the SBD or the transistor, there is a large reduction in storage time.
Thus, transistor switching time is significantly reduced.
A cross sectional area of the Schottky diode is shown in Figure 5.
COMPARING THE COMPARATORS
Presently available comparator ICs range from the ultra fast
SE/NE521 to the general purpose comparator fashioned from an
inexpensive op amp. Selection of the device depends upon the
application in which it will be used. Speed of conversion is often of
primary importance to minimize pulse position errors of high
frequency signals. At other times the requirements are much less
stringent, allowing the use of a general purpose comparator. A
handy reference guide to the major parameters is summarized in
Figure 6. The necessary parameters can be chosen to select the
proper device.
A general description of the comparator devices is included here to
familiarize the user with available devices and their advantages.
NE/SE521/522 Comparators
Processed with state-of-the-art Schottky barrier diodes, the
NE521/522 series devices provide good input characteristics while
providing the fastest analog-to-TTL conversion to date. Total delay
from input to output is typically 6ns with a guaranteed speed of
12ns. Additional features of this device include the dual
configuration and individual output strobes to simplify system logic.
The NE522, although sacrificing some speed, features
open-collector outputs for party line or wired-OR configurations for
additional system flexibility.
NE/SE527 Comparator
Featuring Darlington inputs for very low bias current, the NE527 is
generically related to the NE529 comparator. Emitter-follower inputs
to the differential amplifier are used to trade better input parameters
for slightly less speed. As Figure 6 shows, a factor of 10
improvement in I
BIAS
is gained with a propagation delay increase of
only 4ns maximum.
NE529 Comparator
The NE529 is manufactured using Schottky technology. Although a
few nanoseconds slower than the NE521, the NE529 features
variable supplies from
±
5 to
±
10V with a high common-mode range
of
±
6V. Both the NE527 and NE529 Schottky comparators boast
complementary logic outputs with output A being in phase with input
A. In addition, the supplies of both the NE527 and NE529 may be
non-symmetrical to produce a desired shift in the common-mode
range.
This technique is illustrated by the ECL-to-TTL and TTL-to-ECL
transistor of Figures 16 and 17, respectively. The only major
requirement of the supplies is that the negative supply be at least 5V
more negative than the ground terminal of the gate. This is
necessary to insure that the internal bias arrangement has sufficient
voltage to operate normally.
APPLICATIONS
Today’s state-of-the-art ultra high-speed comparators are capable of
making logic decisions in less than 10ns. They are easily applied
and possess good input and power supply noise rejection. As with
all linear ICs, however, some preliminary steps should be taken in
their use.
GENERAL PRECAUTIONS
Layout
The comparator is capable of resolving sub-millivolt signals. To
prevent unwanted signals from appearing at signal ports, good
physical layout is required. For any high-speed design, ground
planes should be used to guard against ground loops and other
sources of spurious signals. At high frequencies, hidden signal
paths become dominant. Distributed capacitance is a particular
nuisance. If care is not taken to isolate output from input, distributed
capacitance can couple a few millivolts into the input, causing
oscillation.
Another source of spurious signals is ground current. Input
structures are relatively high impedance while the gate structures of
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| EPF10K40RC208-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC208-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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