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| 型号： | EPF10K40 |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10K嵌入式可编程逻辑系列） |
| 文件页数： | 5/10页 |
| 文件大小： | 230K |
| 代理商： | EPF10K40 |
Philips Semiconductors
Application note
AN116
Applications for the NE521/522/527/529
1988 Dec
5
It is important to observe this maximum rating since exceeding the
differential input voltage limit and drawing excessive current in
breaking down the emitter-base junctions of the input transistors
could cause gross degradation in the input offset current and bias
current parameters.
It is also important to note that response time is specified for a
common-mode voltage of zero and may degrade when the
common-mode voltage approaches the common-mode specification
limits.
Exceeding the absolute maximum positive input voltage limit of the
device will saturate the input transistor and possibly cause damage
through excessive current. However, even if the current is limited to
a reasonable value so that the device is not damaged, erratic
operation can result.
Input Impedance
The differential bias and offset currents of comparators are
minimized by design. As was pointed out for op amps, the input
resistance seen by both inputs should be equal. This reduces to a
minimum the contribution of offset current to threshold error.
Unbalanced input impedance also adds to the offset error due to the
difference in voltage drop across the input resistances.
BASIC APPLICATIONS
The basic comparator circuit and its transfer function were
presented by Figure 1.
When the input exceeds the reference voltage, the output switches
either positive or negative, depending on how the inputs are
connected.
The vast majority of specific applications involve only the basic
configuration with a change of reference voltage. A-to-D converters
are realized by applying the signal to one terminal and the voltage
derived from a ladder network to the other. Limit detectors are
likewise made from only the very basic circuit. Both are only a small
deviation from the basic level detector.
Hysteresis
Normally saturated high or low, the amplifiers used in voltage
comparators are seldom held in their threshold region.
They possess high gain-bandwidth products and are not
compensated to preserve switching speed. Therefore, if the
compared voltages remain at or near the threshold for long periods
of time, the comparator may oscillate or respond to noise pulses.
For instance, this is a common problem with successive
approximation D/A converters where the differential voltage seen by
the comparator becomes successively smaller until noise signals
cause indecision. To avoid this oscillation in the linear range,
hysteresis can be employed from output to input. Figure 7 defines
the arrangement. Both positive and negative feedback is provided
by R
IN
and R
F
.
Hysteresis occurs because a small portion of the “one” level output
voltage is fed back in phase and added to the input signal. This
feedback aids the signal in crossing the threshold. When the signal
returns to the threshold, the positive feedback must be overcome by
the signal before switching can occur. The switching process is then
assured and oscillations cannot occur. The threshold “dead zone”
created by this method, illustrated in Figure 8, prevents output
chatter with signals having slow and erratic zero crossings.
As shown in Figure 7, the voltage feedback is calculated from the
expression:
V
HYST
E
OUT
R
IN
R
IN
R
F
where E
OUT
is the gate high output voltage.
The hysteresis voltage is bounded by the common-mode range and
the ability of the gate to source the current required by the feedback
network. If symmetrical hysteresis is desired, an additional inverting
gate is required if the comparator does not have differential outputs.
The NE527 and NE529 devices provide inverted signals from
differential outputs while the NE521 and NE522 devices will require
the inverter. Care should be taken in the selection of the inverter that
propagation delay is minimum, especially for very high-speed
comparators such as the NE521.
NOTE:
VHYST
EOUT
RIN
RIN
RF
R
IN
R
F
V
IN
E
OUT
R
IN
R
F
V
TH
SL00733
Figure 7. Level Detector With Hysteresis
INPUT (10mV/cm)
OUTPUT
1V/cm
SL00734
Figure 8. 0V Level Detector With
±
10mV Hysteresis
Line Receiver
Retrieving signals which have been transmitted over long cables in
the presence of high electrical noise is a perfect application for
differential comparators. Such systems as automated production
lines and large computer systems must transmit high frequency
digital signals over long distances.
If the twisted-pair of the system is driven differentially from ground,
the signals can be reclaimed easily via a differential line receiver.
Since the electrical noise imposed upon a pair of wires takes the
form of a common-mode signal, the very high common-mode
rejection of the NE521/522 makes the unit ideal for differential line
receivers. Figure 9 depicts the simple schematic arrangement. The
NE521 is used as a differential amplifier having a logic level output.
Because common-mode signals are rejected, noise on the cable
disappears and only the desired differential signal remains. Figure
10 illustrates the NE521 response to the 200mV
P-P
10MHz
differential signal. In Figure 11 the same signal has been buried in
5V
P-P
of 1MHz common-mode “noise.”
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参数描述 |
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| EPF10K40RC208-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC208-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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