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| 型号： | EPF10K40 |
| 厂商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family(FLEX10K嵌入式可编程逻辑系列) |
| 中文描述： | 嵌入式可编程逻辑系列（FLEX10K嵌入式可编程逻辑系列） |
| 文件页数： | 8/10页 |
| 文件大小： | 230K |
| 代理商： | EPF10K40 |
Philips Semiconductors
Application note
AN116
Applications for the NE521/522/527/529
1988 Dec
8
–
+
–
+
V
IN
2R
2R
2R
2R
2R
2R
521
521
521
R
521
2R
2R
R/4
OVER
RANGE
V
REF
(3 Vmax)
–
+
–
+
–
+
–
+
–
+
–
+
2
0
(LSB)
2
1
2
2
(MSB)
SL00741
Figure 15. 3-Bit Parallel A/D Converter
Photo Diode Detector
Responding to the presence or absence of light, the photo diode
increases or decreases the current through it. Detecting the
changes becomes a matter of converting light and dark currents to
voltage across a resistor as shown in Figure 18. R1 is selected to be
large enough to generate detectable differences between light and
dark conditions. Once the signal levels are defined by R1 and the
diode characteristics, the average between light and dark signals is
used for V reference and is produced by the resistive divider
consisting of R1 and R2. The comparator then produces an output
dependent upon the presence or absence of light upon the diode.
SENSE AMPLIFIERS
Closely related to the comparator is the sense amplifier. Signals
derived from the many sources, such as transducers, are not of
sufficient amplitude to be compatible with subsequent logic. It then
becomes necessary to amplify and convert the signal to TTL levels,
which is the responsibility of the sense amplifier.
Some transducers produce an output current. It remains, then, for
the user to convert these currents to TTL levels. A terminating
resistor from the drain to ground provides a voltage output
proportional to the current and the resistor size. Larger signals can
be produced by larger resistors; but in practice, resistors larger than
1k
are avoided because of increasing access time. Distributed
capacitance forms a time constant with this output resistance
causing slow rise and fall times when the resistor is large, adding to
the access time.
Virtually any voltage comparator or sense amplifier can be used.
Since total time is the sum of all delays, the sense amplifier is most
often the fastest available. Philips Semiconductors comparators
NE521 and NE522 are ideal in this application because of low input
offset voltages and very fast response. Using these Schottky
clamped comparators significantly reduces the total cycle time of the
memory.
Design of the sense amplifier network depends upon the transducer
used and the input characteristics of the sense amplifier. The
significant specifications are given in Table 1.
Consideration must first be given to the differential input voltage
requirements of the sense amplifier. The required reference voltage
is calculated from the relationship:
V
REF
≤
(I
T
-I
B
)R1-V
DIFF
Where I
T
is the transducer output current, I
B
is sense amplifier bias
current and V
DIFF
is minimum differential voltage to switch the sense
amplifier.
In large systems, noise coupled into the sense lines by stray
capacitance can be very troublesome. Judicious layout patterns with
sense lines as short as possible will help, but will not always be
sufficient. One method of eliminating noise is to use a balance
sense line as shown in Figure 19.
A dummy line should be run parallel to the actual sense line in as
close proximity as possible. One end is connected to the sense
amplifier at the V
REF
point while the other end is left open. The
normal sense line is connected as usual. Electrical noise imposed
upon the pair of sense lines takes the form of a common-mode
signal and will be rejected by the sense amplifier. Signal currents in
the sense line, on the other hand, form differential signals at the
sense amp, causing the output to switch.
Table 1.
Important Sense Amplifier Parameters
DEVICE
V
OS
(mV)
I
B
(
μ
A)
V
IN (MIN)
(mV)
SPEED (ns)
(V
IN
=100mV)
12
GAIN
521
10
40
15
5000
522
10
40
15
15
5000
+ 5V
1
10
9
Q
Q
7
529
5
6
3
2
R1
R1
R2
R2
ECL
INPUT
TTL OUTPUTS
– 10V
SL00742
Figure 16. ECL-to-TTL Translator
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相关代理商/技术参数 |
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| EPF10K40RC208-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC208-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-4 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K40RC240-4N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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