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参数资料
| 型号： | EPF6010A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 1/21页 |
| 文件大小： | 241K |
| 代理商： | EPF6010A |
Altera Corporation
919
Understanding
FLEX 6000 Timing
May 1999, ver. 2
Application Note 92
A-AN-092-02
Introduction
Altera
devices provide predictable performance that is consistent from
simulation to application. Before configuring a device, you can determine
the worst-case timing delays for any design by using the MAX+PLUS
II
Timing Analyzer. You can also calculate the propagation delays by using
the timing model provided in this application note along with the timing
parameters listed in the
FLEX 6000 Programmable Logic Device Family Data
Sheet
in this data book.
1
For the most precise timing results, you should use the
MAX+PLUS II Timing Analyzer, which accounts for the effects
of secondary factors such as placement and fan-out.
This application note defines FLEX
6000 device internal and external
timing parameters, and illustrates the timing model for the FLEX 6000
device family.
Familiarity with the FLEX 6000 architecture and characteristics is
assumed. Refer to the
FLEX 6000 Programmable Logic Device Family Data
Sheet
for a complete description of the FLEX 6000 architecture and for
specific values for timing parameters listed in this application note.
Internal Timing
Micropara-
meters
The timing delays contributed by individual FLEX 6000 architectural
elements are called internal timing microparameters, which cannot be
measured explicitly. All internal timing microparameters are shown in
italic type. The following sections define the internal timing
microparameters for the FLEX 6000 device family.
I/O Element Timing Microparameters
The following list describes the I/O element (IOE) timing
microparameters for the FLEX 6000 device family:
t
OD1
Output buffer and pad delay with the slow slew rate
logic option turned off and V
CCIO
= V
CCINT
.
t
OD2
Output buffer and pad delay with the slow slew rate
logic option turned off and V
CCIO
= low voltage.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6010ATC100-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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