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参数资料
| 型号： | EPF6010A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 3/21页 |
| 文件大小： | 241K |
| 代理商： | EPF6010A |
Altera Corporation
921
AN 92: Understanding FLEX 6000 Timing
t
ROW
Row interconnect routing delay. The delay incurred
by a signal that requires routing through a row
channel in the FastTrack Interconnect. The
t
ROW
delay
is a function of fan-out and the distance between the
source and destination LEs. The value shown in the
FLEX 6000 Programmable Logic Device Family Data Sheet
is the longest delay possible for an LE with a fan-out of
four LEs. However, the value generated by the
MAX+PLUS II Timing Analyzer is more accurate
because it includes fan-out considerations and the
relative locations of the source and destination LEs of
the design.
1
This parameter is a worst-case value for
typical applications. Post-compilation timing
simulation and timing analysis are required to
determine actual worst-case performance.
t
COL
Column interconnect routing delay. The delay
incurred by a signal that requires routing through a
column channel in the FastTrack Interconnect. The
value shown in the
FLEX 6000 Programmable Logic
Device Family Data Sheet
is the longest delay possible
for an LE with a fan-out of four LEs. However, the
value generated by the MAX+PLUS II Timing
Analyzer is more accurate because it includes fan-out
considerations and the relative locations of the source
and destination LEs of the design.
1
This parameter is a worst-case value for
typical applications. Post-compilation timing
simulation and timing analysis are required to
determine actual worst-case performance.
t
DIN_D
Dedicated input to LE data delay. The time required
for a signal, used as a data input, to reach an LE from
a dedicated input pin. The
t
DIN_D
delay is a function of
fan-out and the distance between the source pin and
destination LEs. The value shown in the
Programmable Logic Device Family Data Sheet
longest delay possible for a dedicated input with a
fan-out of four LEs. However, the value generated by
the MAX+PLUS II Timing Analyzer is more accurate
because it includes fan-out considerations and the
relative locations of the source and destination LEs of
the design.
FLEX 6000
is the
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6010ATC100-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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