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参数资料
| 型号： | EPF6010A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 13/21页 |
| 文件大小： | 241K |
| 代理商： | EPF6010A |
Altera Corporation
931
AN 92: Understanding FLEX 6000 Timing
Figure 2. Logic Element External Timing Parameters (Part 4 of 4)
Timing Model
vs.
MAX+PLUS II
Timing
Analyzer
Hand calculations based on the timing model provide a good estimate of
a design’s performance. However, the MAX+PLUS II Timing Analyzer
always provides the most accurate information on the performance of a
design because it takes into account three secondary factors that influence
the routing microparameters:
I
I
I
Fan-out for each signal in the delay path
Positions of other loads relative to the source and destination
Distance between signal source and destination
Fan-Out
The more loads a signal has to drive, the longer the delay across
t
ROW
,
t
COL
,
and
t
DIN_D
. These delays are functions of the number of LABs that a
signal source must drive.
Load Distribution
The load distribution relative to the source and destination also affects the
t
ROW
,
t
COL
, and
t
DIN_D
delays. Consider a signal
s1
that feeds destination
d1
and logic elements
y[4..1]
. If
y[4..1]
are in different LABs,
s1
has
four additional loads. However, if the LEs are all in the same LAB,
s1
has
one shorter-delay load. Therefore, the row interconnect delay from
s1
to
d1
is greater when each load
y[4..1]
is in a different LAB.
Figure 3
illustrates how variations in the position of
d1
and the distribution of
y[4..1]
change the routing delay.
Setup Time from a Global Clock & Row I/O Data Input
t
SU
=
[(t
IN
+ t
ROW
+ t
LOCAL
+ t
DATA_TO_REG
) – (t
DIN_C
+ t
C
)] + t
SU
Hold Time from a Global Clock & Row I/O Data Input
t
H
=
[(t
DIN_C
+ t
C
) – (t
IN
+ t
ROW
+ t
LOCAL
+ t
DATA_TO_REG
)] + t
H
Row I/O
Dedicated Clock
LE Register
Combinatorial
Logic
Row I/O
Dedicated Clock
LE Register
Combinatorial
Logic
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6010ATC100-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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