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| 型号： | EPF6010A |
| 厂商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可编程逻辑系列器件) |
| 中文描述： | 可编程逻辑器件系列（FLEX6000可编程逻辑系列器件） |
| 文件页数： | 5/21页 |
| 文件大小： | 241K |
| 代理商： | EPF6010A |
Altera Corporation
923
AN 92: Understanding FLEX 6000 Timing
Logic Element Timing Microparameters
The following list describes the LE timing microparameters for the
FLEX 6000 device family:
t
REG_TO_REG
Look-up table (LUT) delay for LE register feedback in
counter mode. The delay incurred by a signal that is
routed from the data output of an LE register back to
the data input of the same LE register. The first LE of
a counter implemented with carry chains incurs a
t
REG_TO_REG
delay.
t
CASC_TO_REG
Cascade-in to register delay. The delay from the
cascade-in signal to the data input of the LE register.
t
CARRY_TO_REG
Carry-in to register delay. The delay from the carry-in
signal to the data input of the LE register.
t
DATA_TO_REG
LE input to register delay. The delay from the LE data
input signal through the LUT to the data input of the
LE register.
t
CASC_TO_OUT
Cascade-in to LE output delay. The delay from the
cascade-in signal to the output of the LE.
t
CARRY_TO_OUT
Carry-in to LE output delay. The delay from the
carry-in signal to the output of the LE.
t
DATA_TO_OUT
LE input to LE output delay. The time required for an
LE data input signal to propagate through the LUT,
bypass the register, and arrive at the output of the LE.
t
REG_TO_OUT
Register output to LE output delay. The delay from
the output of the LE register to the output of the LE.
t
SU
LE register setup time before clock. The minimum time
that the data input signal is required to be stable at the
LE register input before the register clock’s rising edge
to ensure that the register correctly stores the input
data.
t
SU
is also the minimum recovery time between
deasserting the clear signal and the rising edge of the
clock.
t
H
LE register hold time after clock. The minimum time
that a signal is required to be stable at the LE register
input after the register clock’s rising edge to ensure
that the register correctly stores the input data.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF6010ATC100-1 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-1N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-2 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF6010ATC100-3 | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 6000 88 LABs 71 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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