参数资料
型号: EPM7256SRI208-10N
厂商: Altera
文件页数: 10/66页
文件大小: 0K
描述: IC MAX 7000 CPLD 256 208-RQFP
产品变化通告: Package Change 30/Jun/2010
标准包装: 24
系列: MAX® 7000
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 4.5 V ~ 5.5 V
逻辑元件/逻辑块数目: 16
宏单元数: 256
门数: 5000
输入/输出数: 164
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 208-BFQFP 裸露焊盘
供应商设备封装: 208-RQFP(28x28)
包装: 托盘
18
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000S Device
The time required to program a single MAX 7000S device in-system can
be calculated from the following formula:
where: tPROG
= Programming time
tPPULSE
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
CyclePTCK =Number of TCK cycles to program a device
fTCK
= TCK frequency
The ISP times for a stand-alone verification of a single MAX 7000S device
can be calculated from the following formula:
where: tVER
=Verify time
tVPULSE
= Sum of the fixed times to verify the EEPROM cells
CycleVTCK =Number of TCK cycles to verify a device
tPROG
tPPULSE
CyclePTCK
fTCK
--------------------------------
+
=
tVER
tVPULSE
CycleVTCK
fTCK
--------------------------------
+
=
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