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参数资料
| 型号： | EV-ADF4157SD1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4157 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4157 |
| 主要属性： | 单路分数-N PLL |
| 次要属性： | 6GHz |
| 已供物品： | 板 |
ADF4157
Data Sheet
Rev. D | Page 16 of 24
FUNCTION REGISTER (R3) MAP
With R3[2:0] set to 011, the on-chip function register is
programmed as shown in Figure 20.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
Σ-Δ Reset
For most applications, DB14 should be set to 0. When DB14 is
set to 0, the Σ-Δ modulator is reset on each write to Register 0.
If it is not required that the Σ-Δ modulator be reset on each
Register 0 write, this bit should be set to 1.
Lock Detect Precision (LDP)
When DB[7] is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
Phase Detector Polarity
DB[6] sets the phase detector polarity. When the VCO
characteristics are positive, this should be set to 1. When they
are negative, it should be set to 0.
RF Power-Down
DB[5] provides the programmable power-down mode. Setting
this bit to 1 performs a power-down. Setting this bit to 0 returns
the synthesizer to normal operation. While in software power-
down mode, the part retains all information in its registers.
Only when supplies are removed are the register contents lost.
When a power-down is activated, the following events occur:
All active dc current paths are removed.
The synthesizer counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RFINx input is debiased.
The input shift register remains active and capable of
loading and latching data.
RF Charge Pump Three-State
DB[4] puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
RF Counter Reset
DB[3] is the RF counter reset bit for the ADF4157. When this
is 1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
DB31
RESERVED
PD
P
OLA
R
ITY
L
DP
CO
UNT
E
R
ESET
CP
T
H
R
EE-ST
A
T
E
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
U12
0
U11
U10
U9
U8
U7
C3(0) C2(1) C1(1)
U9
POWER-DOWN
0
DISABLED
1
ENABLED
U11
LDP
0
24 PFD CYCLES
1
40 PFD CYCLES
U7
COUNTER
RESET
0
DISABLED
1
ENABLED
U10
PD POLARITY
0
NEGATIVE
1
POSITIVE
U8
CP
THREE-STATE
0
DISABLED
1
ENABLED
05874-
014
SD
R
ESET
RESERVED
U12
SD RESET
0
ENABLED
1
DISABLED
Figure 20. Function Register (R3) Map
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