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参数资料
| 型号： | EV-ADF4360-9EB1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4360-9 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-9 |
| 主要属性： | 带 VCO 的单路整数-N PLL |
| 次要属性： | 360MHz，1.6MHz PFD |
| 已供物品： | 板，缆线，CD |
ADF4360-9
Data Sheet
Rev. C | Page 14 of 24
DB20 DB19
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
PC1
PC2
CR
D1
D2
PDP
CP
CPG
MTLD
PL1
PL2
CPI1
CPI2
CPI3
CPI4
CPI5
CPI6
PD1
D3
CONTROL
BITS
DIVOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
DB21
DB22
DB23
PO
W
ER
-
DO
W
N
2
PO
W
ER
-
DO
W
N
1
CO
UNT
E
R
ESET
M
U
TE
-TILL-
LD
R
ESER
VED
R
ESER
VED
CP
G
AI
N
CP
T
HRE
E
-
S
TA
TE
P
HAS
E
D
E
TE
C
TOR
P
OLA
R
ITY
PD2
RSV
CR
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
PC2
0
1
0
CORE POWER LEVEL
2.5mA
5mA (RECOMMENDED)
7.5mA
PC1
0
1
10mA
CP
0
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
PDP
0
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
CPG
0
1
CP GAIN
CURRENT SETTING 1
CURRENT SETTING 2
MTLD
0
1
MUTE-TIL-LOCK DETECT
DISABLED
ENABLED
D3
D2
D1
MUXOUT
DVDD
0
1
0
1
0
1
0
1
0
1
0
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DVDD
R DIVIDER OUTPUT
A CNTR/2 OUT
A CNTR OUT
DGND
CE PIN
PD2
PD1
MODE
0
X
ASYNCHRONOUS POWER-DOWN
1
X
0
NORMAL OPERATION
1
0
1
ASYNCHRONOUS POWER-DOWN
1
SYNCHRONOUS POWER-DOWN
CPI6
CPI5
CPI4
ICP (mA)
CPI3
CPI2
CPI1
4.7k
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PL2
PL1
OUTPUT POWER LEVEL
CURRENT USING TUNED LOAD
–9dBm
–6dBm
–3dBm
0dBm
USING 50 TO VVCO
–19dBm
–15dBm
–12dBm
–9dBm
0
1
0
1
0
1
3.5mA
5.0mA
7.5mA
11.0mA
07139-
022
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
Figure 23. Control Latch
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