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参数资料
| 型号： | EV-ADF4360-9EB1Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4360-9 |
| 标准包装： | 1 |
| 主要目的： | 计时，频率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4360-9 |
| 主要属性： | 带 VCO 的单路整数-N PLL |
| 次要属性： | 360MHz，1.6MHz PFD |
| 已供物品： | 板，缆线，CD |
ADF4360-9
Data Sheet
Rev. C | Page 16 of 24
DB20 DB19
DB18 DB17 DB16 DB15 DB14
DB13 DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
R1
R2
R3
R4
R5
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
LDP
TMB
BSC1
R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21
DB22
DB23
LOC
K
DE
T
E
CT
PR
EC
ISI
O
N
T
EST
M
O
DE
BI
T
R
ESE
R
VED
R
ESE
R
VED
BSC2
RSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14
R13
R12
R3
R2
R1
DIVIDE RATIO
..........
0
1
..........
0
1
0
2
..........
0
1
3
..........
1
0
4
..........
.
..........
.
..........
.
..........
1
0
16380
..........
1
0
1
16381
..........
1
0
16382
..........
1
16383
THESE BITS ARE
NOT USED BY
THE DEVICE
AND ARE DON'T
CARE BITS.
07139-
024
LDP
LOCK DETECT PRECISION
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
ABP2
ABP1
ANTIBACKLASH PULSE WIDTH
0
3.0ns
0
1
1.3ns
1
0
6.0ns
1
3.0ns
BSC2
BSC1
BAND SELECT CLOCK DIVIDER
0
1
0
1
2
1
0
4
1
8
Figure 25. R Counter Latch
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