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参数资料
| 型号： | EVAL-AD2S1200SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD2S1200 |
| 标准包装： | 1 |
| 主要目的： | 接口，旋转变压至数字 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD2S1200 |
| 主要属性： | 图形用户界面（GUI） |
| 已供物品： | 板，CD，电源 |
AD2S1200
Rev. 0 | Page 20 of 24
CLOCK REQUIREMENTS
To achieve the specified dynamic performance, an external
crystal of 8.192 MHz must be used at the CLKIN, XTALOUT
pins. The position and velocity accuracy are guaranteed for
operation with a 8.192 MHz clock. However, the position
accuracy will still be maintained for clock frequencies ±10%
around this value. The velocity outputs are scaled in proportion
to the clock frequency so that if the clock is 10% higher than the
nominal, the full-scale velocity will be 10% higher than
nominal. The maximum tracking rate and the tracking loop
bandwidth also vary with the clock frequency.
CONNECTING TO THE DSP
The AD2S1200 serial port is ideally suited for interfacing to
DSP configured microprocessors. Figure 16 shows the
AD2S1200 interfaced to ADMC401, one of the DSP based
motor controllers.
The on-chip serial port of the ADMC401 is used in the
following configuration:
Alternate framing transmit mode with internal framing
(internally inverted)
Normal framing receive mode with external framing
(internally inverted)
Internal serial clock generation
In this mode, the ADMC401 uses the internal TFS signal as
external RFS to fully control the timing of receiving data and it
uses the same TFS as RD to the AD2S1200. The ADMC401 also
provides an internal continuous serial clock to the AD2S1200.
The SAMPLE signal on the AD2S1200 could be provided either
by using a PIO or by inverting the PWMSYNC signal to
synchronize the position and velocity reading with the PWM
switching frequency. CS and RDVEL may be obtained using two
PIO outputs of the ADMC401. The 12 bits of significant data
plus status bits are available on each consecutive negative edge
of the clock following the low going of the RD signal. Data is
clocked from the AD2S1200 into the data receive register of the
ADMC401. This is internally set to 16 bits (12 bits data, 4 status
bits) because 16 bits are received overall. The serial port
automatically generates an internal processor interrupt. This
allows the ADMC401 to read 16 bits at once and continue
processing.
All ADMC401 products can interface to the AD2S1200 with
similar interface circuitry.
04406-0-016
SCLK
DR
TFS
RFS
PWMSYNC
PIO
SCLK
SOE
SO
RD
SAMPLE
CS
RDVEL
ADMC401
AD2S1200
Figure 16. Connecting to the ADMC401
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