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参数资料
| 型号： | EVAL-AD2S1200SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD2S1200 |
| 标准包装： | 1 |
| 主要目的： | 接口，旋转变压至数字 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD2S1200 |
| 主要属性： | 图形用户界面（GUI） |
| 已供物品： | 板，CD，电源 |
AD2S1200
Rev. 0 | Page 10 of 24
Signal Degradation Detection
Degradation of signal (DOS) is detected when either resolver
input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold
by comparing the monitor signal to a fixed maximum value.
DOS is also detected when the amplitude of the input signals
Sin and Cos mismatch by more than the specified DOS Sin/
Cos mismatch by continuously storing the minimum and
maximum magnitude of the monitor signal in internal registers,
and calculating the difference between the minimum and
maximum. DOS is indicated by a logic low on the DOS pin, and
is not latched when the input signals exceed the maximum
input level. When DOS is indicated due to mismatched signals,
the output is latched low until a rising edge of SAMPLE resets
the stored minimum and maximum values. The DOS condition
has priority over the LOT condition, as shown in Table 4. DOS
is indicated within 30° of angular output error worst case.
Loss of Position Tracking Detection
Loss of tracking (LOT) is detected for three separate conditions:
When the internal error signal of the AD2S1200 has
exceeded 5°
When the input signal exceeds the maximum tracking rate
of 60,000 rpm (1,000 rps)
When the internal position (at the position integrator)
differs from the external position (at the position register)
by more than 5°
LOT is indicated by a logic low on the LOT pin, and is not
latched. LOT has a 4° hysteresis, and is not cleared until the
internal error signal or internal/external position mismatch is
less than 1°. When the maximum tracking rate is exceeded, LOT
is cleared when both the velocity is less than 1,000 rps and the
internal/external position mismatch is less than 1°. LOT can be
indicated for step changes in position (such as after a RESET
signal is applied to the AD2S1200), or for accelerations
>~85,000 rps2. LOT is useful as a built-in test (BIT) that the
tracking converter is functioning properly. The LOT condition
has lower priority than both the DOS and LOS conditions as
shown in Table 4. The LOT and DOS conditions cannot be
indicated at the same time.
Table 4. Fault Detection Decoding
Condition
DOS
LOT
Priority
Loss of Signal
0
1
Degradation of Signal
0
1
2
Loss of Tracking
1
0
3
No Fault
1
Responding to a Fault Condition
If any fault condition (LOS, DOS, or LOT) is indicated by the
AD2S1200, the output data must be presumed to be invalid.
This means that even if a RESET or SAMPLE pulse releases the
fault condition, the output data may be corrupted, even though
a fault may not be immediately indicated after the RESET/
SAMPLE event. As discussed earlier, there are some fault
conditions with inherent latency. If the device fault is cleared,
there could be some latency in the resolver’s mechanical
position before the fault condition is re-indicated.
When a fault is indicated, all output pins will still provide data,
although the data may or may not be valid. The fault condition
will not force the parallel, serial, or encoder outputs to a known
state. However, a new startup sequence is recommended only
after a LOS fault has been indicated.
Response to specific fault conditions is a system-level
requirement. The fault outputs of the AD2S1200 indicate that
the device has sensed a potential problem with either the
internal or external signals of the AD2S1200. It is the
responsibility of the system designer to implement the
appropriate fault-handling schemes within the control hardware
and/or algorithm of a given application based on the indicated
fault(s) and the velocity or position data provided by the
AD2S1200.
False Null Condition
Resolver-to-digital converters that employ Type II tracking
loops based on the error equation (Equation 3) presented in the
Principle of Operation section can suffer from a condition
known as “false null.” This condition is caused by a metastable
solution to the error equation when θ = 180°. The
AD2S1200 is not susceptible to this condition because its
hysteresis is implemented externally to the tracking loop.
Because of the loop architecture chosen for the AD2S1200, the
internal error signal always has some movement (1 LSB per
clock cycle), and so, in a metastable state, the converter will
always move to an unstable condition within one clock cycle,
causing the tracking loop to respond to the false null condition
as if it were a 180° step change in input position (the response
time is the same as specified in Dynamic Performance section
of Table 1). Therefore, it is impossible to enter the metastable
condition any time after the startup sequence as long as the
resolver signals are valid. However, in a case of a loss of signal, a
full reset is recommended to avoid the possibility of a false null
condition. The response to the false null condition has been
Sequencing and Reset section.
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