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参数资料
| 型号： | EVAL-AD5064-1EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5064-1 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| 系列： | nanoDAC™ |
| DAC 的数量： | 4 |
| 位数： | 16 |
| 采样率（每秒）： | 125k |
| 数据接口： | 串行 |
| 设置时间： | 8µs |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 125°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD5064 |
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AD5024/AD5044/AD5064
Data Sheet
Rev. F | Page 22 of 28
POWER-ON RESET
The AD5024/AD5044/AD5064/AD5064-1 contain a power-on
reset circuit that initializes the registers to their default values
and controls the output voltage during power-up. By connecting
the POR pin low, the AD5024/AD5044/AD5064/AD5064-1
output powers up to zero scale. Note that this is outside the
linear region of the DAC; by connecting the POR pin high, the
AD5024/AD5044/AD5064/AD5064-1 output powers up to
midscale. The output remains powered up at this level until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
There is also a software executable reset function that resets the
DAC to the power-on reset code. Command 0111 is designated
for this reset function (see Table 8). Any events on LDAC or
CLR during power-on reset are ignored. The power-on reset
circuit is triggered when VDD passes 2.6 V approximately and
takes 50 s to complete. No writes to the AD5024/AD5044/
AD5064/AD5064-1 should take place during this time. For
applications which have a slow VDD ramp time (for example,
more than 2 ms to 3ms), it is recommended that a software
reset command is written when the power supplies have
reached their final value.
POWER-DOWN MODES
The AD5024/AD5044/AD5064/AD5064-1 contain three
separate power-down modes. Command 0100 is designated for
the power-down function (see Table 8). These power-down
modes are software-programmable by setting two bits, Bit DB9
and Bit DB8, in the shift register. Table 12 shows how the state of
the bits corresponds to the mode of operation of the device.
Table 12. Modes of Operation
DB9
DB8
Operating Mode
0
Normal operation
Power-down modes:
0
1
1 k to GND
1
0
100 k to GND
1
Three-state
Any or all DACs (DAC D to DAC A) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, DB0) to 1. See Table 13 for the contents of the shift
register during power-down/power-up operation.
When both Bit DB9 and Bit D8 in the shift register are set to 0,
the part works normally with its normal power consumption of
4 mA at 5 V. However, for the three power-down modes, the
supply current falls to 0.4 μA at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different power-down options. The output is connected inter-
nally to GND through either a 1 k or a 100 k resistor, or it is
left open-circuited (three-state). The output stage is illustrated in
RESISTOR
NETWORK
VOUT
DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
06803-
011
Figure 51. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The DAC register can be
updated while the device is in power-down mode. The time to
Table 13. 32-Bit Shift Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB31
to
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
to
DB10
DB9
DB8
DB7
to
DB4
DB3
DB2
DB1
DB0
X
0
1
0
X
PD1
PD0
X
DAC D
DAC C
DAC B
DAC A
Don’t
cares
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Power-
down mode
Don’t
cares
Power-down/power-up channel
selection—set bit to 1 to select
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