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| 型号： | EVAL-AD5425EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/25页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5425 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| DAC 的数量： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 2.47M |
| 数据接口： | 串行 |
| 设置时间： | 15ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5425 |
| 相关产品： | AD5425YRMZ-REEL7-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRMZ-REEL-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRMZ-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRM-REEL7-ND - IC DAC 8BIT MULTIPLYING 10-MSOP AD5425YRM-REEL-ND - IC DAC 8BIT MULTIPLYING 10-MSOP AD5425YRM-ND - IC DAC MULTIPLYING 8BIT 10-MSOP |
AD5425
Data Sheet
Rev. C | Page 14 of 24
THEORY OF OPERATION
The AD5425 is an 8-bit current output DAC consisting of a
standard inverting R-2R ladder configuration. A simplified
value of R. The value of R is typically 10 k (minimum 8 k
and maximum 12 k). If IOUT1 and IOUT2 are kept at the same
potential, a constant current flows in each ladder leg, regardless
of digital input code. Therefore, the input resistance presented
at VREF is always constant and nominally of value R. The DAC
output, IOUT, is code-dependent, producing various resistances
and capacitances. When choosing the external amplifier, take
into account the variation in impedance generated by the DAC
on the amplifiers inverting input node.
Figure 29. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals
of the DAC, making the device extremely versatile and
allowing it to be configured in several different operating
modes, for example, to provide a unipolar output, bipolar
output, or in single-supply modes of operation in unipolar
mode or 4-quadrant multiplication in bipolar mode. Note
that a matching switch is used in series with the internal RFB
feedback resistor. If users attempt to measure RFB, power must
be applied to VDD to achieve continuity.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, this device can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 30.
When an output amplifier is connected in unipolar mode, the
output voltage is given by
n
REF
OUT
D
V
2
×
=
where D is the fractional representation of the digital word
loaded to the DAC, in this case 0 to 255, and n is the number
of bits.
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
This DAC is designed to operate with either negative or positive
reference voltages. The VDD power pin is used by only the inter-
nal digital logic to drive the DAC switches’ on and off states.
This DAC is also designed to accommodate ac reference input
signals in the range of 10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 30 gives
a unipolar 0 V to 10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation.
Table 5. Unipolar Code Table
Digital Input
Analog Output (V)
1111 1111
V
REF (255/256)
1000 0000
V
REF (128/256) = VREF/2
0000 0001
V
REF (1/256)
0000 0000
V
REF (0/256) = 0
Figure 30. Unipolar Operation
VREF
IOUT2
DAC DATA LATCHES
AND DRIVERS
IOUT1
RFB
2R
S1
2R
S2
2R
S3
2R
S8
R
03161-
029
VOUT = 0
TO –VREF
SCLK SDIN GND
VREF
SYNC
IOUT2
IOUT1
RFB
AGND
AD5425
R1
R2
A1
VREF
VDD
C1
NOTES:
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
MICROCONTROLLER
03161-030
A1
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