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参数资料
| 型号： | EVAL-AD7492SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7492 |
| 标准包装： | 1 |
| 系列： | * |
AD7492
Rev. A | Page 18 of 24
GROUNDING AND LAYOUT
The analog and digital power supplies are independent and
separately pinned out to minimize coupling between analog and
digital sections within the device. To complement the excellent
noise performance of the AD7492, it is imperative that care be
given to the PCB layout. Figure 28 shows a recommended
connection diagram for the AD7492.
All of the AD7492 ground pins should be soldered directly to a
ground plane to minimize series inductance. The AVDD pin,
DVDD pin, and VDRIVE pin should be decoupled to both the
analog and digital ground planes. The REF OUT pin should be
decoupled to the analog ground plane with a minimum
capacitor value of 100 nF. This capacitor helps to stabilize the
internal reference circuit. The large value capacitors decouple
low frequency noise to analog ground, the small value
capacitors decouple high frequency noise to digital ground. All
digital circuitry power pins should be decoupled to the digital
ground plane. The use of ground planes can physically separate
sensitive analog components from the noisy digital system. The
two ground planes should be joined in only one place and
should not overlap so as to minimize capacitive coupling
between them. If the AD7492 is in a system where multiple
devices require AGND-to-DGND connections, the connection
should still be made at one point only, a star ground point,
established as close as possible to the AD7492.
AD7492
+
1nF
+
100nF
AGND
DGND
REF OUT
+
2.5V
ANALOG
SUPPLY
5V
47F
0.1F
10F
AVDD
DVDD
VDRIVE
01
12
8
-02
8
Figure 28. Typical Decoupling Circuit
Noise can be minimized by applying the following simple rules
to the PCB layout:
Analog signals should be kept away from digital signals.
Fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections of
the board and clock signals should never be run near the
analog inputs.
Avoid running digital lines under the device as this couples
noise onto the die.
The power supply lines to the AD7492 should use as large a
trace as possible to provide a low impedance path and reduce
the effects of glitches on the power supply line.
Avoid crossover of digital and analog signals and place
traces that are on opposite sides of the board at right angles
to each other.
Noise to the analog power line can be further reduced by use of
multiple decoupling capacitors as shown in Figure 28.
Decoupling capacitors should be placed directly at the power
inlet to the PCB and also as close as possible to the power pins
of the AD7492. The same decoupling method should be used
on other ICs on the PCB, with the capacitor leads as short as
possible to minimize lead inductance.
POWER SUPPLIES
Separate power supplies for AVDD and DVDD are desirable, but if
necessary, DVDD can share its power connection to AVDD. The
digital supply (DVDD) must not exceed the analog supply (AVDD)
by more than 0.3 V in normal operation.
MICROPROCESSOR INTERFACING
ADSP-2185 to AD7492 Interface
Figure 29 shows a typical interface between the AD7492 and the
ADSP-2185. The ADSP-2185 processor can be used in one of
two memory modes, full memory mode and host mode. The
Mode C pin determines in which mode the processor works.
The interface in Figure 29 is set up to have the processor
working in full memory mode, allowing full external addressing
capabilities.
When the AD7492 has finished converting, the BUSY line
requests an interrupt through the IRQ2 pin. The IRQ2 interrupt
has to be set up in the interrupt control register as edge-
sensitive. The data memory select (DMS) pin latches in the
address of the ADC into the address decoder. The read
operation is started.
ADDRESS BUS
DATA BUS
100k
1ADDITIONAL PINS OMITTED FOR CLARITY.
OPTIONAL
ADDRESS
DECODER
AD7492
BUSY
DB0 TO DB9
(DB11)
CONVST
CS
RD
ADSP-21851
DMS
IRQ2
RD
MODE C
D0 TO D23
A0 TO A15
01
12
8-
0
29
Figure 29. ADSP-2185 to AD7492 Interface
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