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参数资料
| 型号： | EVAL-AD7492SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7492 |
| 标准包装： | 1 |
| 系列： | * |
AD7492
Rev. A | Page 6 of 24
TIMING SPECIFICATIONS
Table 3.
Limit at TMIN, TMAX
Parameter
AD7492/AD7492-4
AD7492-52
Unit
Description
tCONVERT
880
680
ns max
tWAKEUP
203
μs max
Partial Sleep Wake-Up Time
500
μs max
Full Sleep Wake-Up Time
t1
10
ns min
CONVST Pulse Width
t2
10
ns max
CONVST to BUSY Delay, VDD = 5 V
40
N/A
ns max
CONVST to BUSY Delay, VDD = 3 V
t3
0
ns max
BUSY to CS Setup Time
t44
0
ns max
CS to RD Setup Time
t5
20
ns min
RD Pulse Width
t64
15
ns min
Data Access Time after Falling Edge of RD
t75
8
ns max
Bus Relinquish Time after Rising Edge of RD
t8
0
ns max
CS to RD Hold Time
t9
120
ns min
Acquisition Time
t10
100
ns min
Quiet Time
1 Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2).
2 The AD7492-5 is specified with VDD = 4.75 V to 5.25 V.
3 This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part
samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time.
4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V
5 t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
1.6V
200A
IOL
TO OUTPUT
PIN
CL
50pF
200A
IOH
0
11
28-
0
02
Figure 2. Load Circuit for Digital Output Timing Specifications
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