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| 型号： | EVAL-AD7492SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7492 |
| 标准包装： | 1 |
| 系列： | * |
AD7492
Rev. A | Page 15 of 24
BUSY
CS
RD
DBx
CONVST
t10
t9
t3
t4
t5
t8
t6
t7
tCONVERT
t2
01
12
8-
0
19
Figure 19. Parallel Port Timing
CONVST
BUSY
DBx
tCONVERT
t2
t9
DATA N
DATA N+1
01
12
8-
0
20
Figure 20. Parallel Port Timing with CS and RD Tied Low
Mode 2 (Partial or Full Sleep Mode)
Figure 21 shows the AD7492 in Mode 2 operation where the
ADC goes into either partial or full sleep mode after
conversion. The CONVST line is brought low to initiate a
conversion and remains low until after the end of the
conversion. If CONVST goes high and low again while BUSY is
high, the conversion is restarted. Once the BUSY line goes from
high-to-low, the CONVST line has its status checked and, if low,
the part enters a sleep mode. The type of sleep mode the
AD7492 enters depends on what way the PS/FS pin is
hardwired. If the PS/FS pin is tied high, the AD7492 enters
partial sleep mode. If the PS/FS pin is tied low, the AD7492
enters full sleep mode.
The device wakes up again on the rising edge of the CONVST
signal. From partial sleep the AD7492 is capable of starting
conversions typically 1 μs after the rising edge of CONVST. The
CONVST line can go from high-to-low during the wake-up time,
but the conversion is still not initiated until after 1 μs. It is
recommended that the conversion should not be initiated until at
least 20 μs of the wake-up time has elapsed. This ensures that the
AD7492 has stabilized to within 0.5 LSB of the analog input value.
After 1 μs, the AD7492 has only stabilized to within approxi-
mately 3 LSB of the input value. From full sleep, this wake-up
time is typically 500 μs. In all cases the BUSY line only goes high
once CONVST goes low. Superior power performance can be
achieved in these modes of operation by waking up the AD7492
only to carry out a conversion. The optimum power performance
is obtained when using full sleep mode as the ADC comparator,
reference buffer, and reference circuit are powered down. While
in partial sleep mode, only the ADC comparator is powered
down and the reference buffer is put into a low power mode. The
100 nF capacitor on the REF OUT pin is kept charged up by the
reference buffer in partial sleep mode while in full sleep mode
this capacitor slowly discharges. This explains why the wake-up
time is shorter in partial sleep mode. In both sleep modes the
clock oscillator circuit is powered down.
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