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| 型号： | EVAL-AD7731EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7731 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | 串行 |
| 输入范围： | ±1.28 V |
| 在以下条件下的电源（标准）： | 67.5mW @ 6.4kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7731 |
| 已供物品： | 板，CD |
| 相关产品： | AD7731BNZ-ND - IC ADC 24BIT SIGMA-DELTA 24DIP AD7731BRUZ-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRUZ-REEL-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRUZ-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRZ-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRZ-REEL-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRZ-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRU-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRU-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BR-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC 更多... |
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AD7731
–19–
REV. 0
Table XV. SF Ranges
CHOP
SKIP
SF Range
Output Update Rate Range (Assuming 4.9152 MHz Clock)
0
2048 to 150
150 Hz to 2.048 kHz
1
0
2048 to 75
50 Hz to 1.365 kHz
0
1
2048 to 40
150 Hz to 7.6 kHz
1
2048 to 20
50 Hz to 5.12 kHz
Bit
Location
Mnemonic
Description
FR3
ZERO
A zero must be written to this bit to ensure correct operation of the AD7731.
FR2
CHP
Chop Enable Bit. This bit determines if the chopping mode on the part is enabled. A 1 in this
bit location enables chopping on the part. When the chop mode is enabled, the part is effec-
tively chopped at its input and output to remove all offset and offset drift errors on the part.
If offset performance with time and temperature are important parameters in the design, it is
recommended that the user enable chopping on the part.
FR1
SKIP
FIR Filter Skip Bit. With a 0 in this bit, the AD7731 performs two stages of filtering before
shipping a result out of the filter. The first is a Sinc
3 filter followed by a 22-tap FIR filter.
With a 1 in this bit, the FIR filter on the part is bypassed and the output of the Sinc
3 is fed
directly as the output result of the AD7731’s filter (see Filter Architecture for more details on
the filter implementation).
FR0
FAST
FASTStep Mode Enable Bit. A 1 in this bit enables the FASTStep mode on the AD7731. In
this mode, if a step change on the input is detected, the FIR calculation portion of the filter is
suspended and replaced by a simple moving average on the output of the Sinc
3 filter. Ini-
tially, two outputs from the sinc3 filter are used to calculate an AD7731 output. The number
of sinc
3 outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to
16) until the
STDY bit goes low. When the FIR filter has fully settled after a step, the STDY
bit will become active and the FIR filter is switched back into the processing loop (see Filter
Architecture section for more details on the FASTStep mode).
Offset Calibration Register (RS2–RS0 = 1, 0, 1)
The AD7731 contains three 24-bit Offset Calibration Registers, labeled Offset Calibration Register 0 to Offset Calibration Register
2, to which data can be written and from which data can be read. The three registers are totally independent of each other such that
in fully-differential mode there is an offset register for each of the input channels. This register is used in conjunction with the associ-
ated Gain Calibration Register to form a register pair. The calibration register pair used to scale the output of the filter is as outlined
in Table XIII. To access the appropriate Offset Calibration Register the user should write first to the Mode Register setting up the
appropriate address in the CH2 to CH0 bits.
The Offset Calibration Register is updated after an offset calibration routine (1, 0, 0 or 1, 1, 0 loaded to the MD2, MD1, MD0 bits
of the Mode Register). During subsequent conversions, the contents of this register are subtracted from the filter output prior to gain
scaling being performed on the word. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a
flowchart for writing to the registers on the part.
Gain Calibration Register (RS2–RS0 = 1, 1, 0)
The AD7731 contains three 24-bit Gain Calibration Registers to which data can be written and from which data can be read. The
three registers are totally independent of each other such that in fully-differential mode there is a gain register for each of the input
channels. This register is used in conjunction with the associated Offset Calibration Register to form a register pair which scale the
output of the filter before it is loaded to the Data Register. These register pairs are associated with input channel pairs as outlined in
Table XIII. To access the appropriate Gain Calibration Register the user should write first to the Mode Register setting up the ap-
propriate address in the CH2 to CH0 bits.
The Gain Calibration Register is updated after a gain calibration routine (1, 0, 1 or 1, 1, 1 loaded to the MD2, MD1, MD0 bits of
the Mode Register). During subsequent conversions, the contents of this register are used to scale the number which has already
been offset corrected with the Offset Calibration Register contents. Figure 5 shows a flowchart for reading from the registers on the
AD7731 and Figure 6 shows a flowchart for writing to the registers on the part.
Test Register (RS2–RS0 = 1, 1, 1); Power On/Reset Status: 000000Hex
The AD7731 contains a 24-bit Test Register to which data can be written and from which data can be read. The contents of this
register are used in testing the device. The user is advised not to change the status of any of the bits in this register from the default
(Power-On or
RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the part
enters one of its test modes, exercising
RESET or writing 32 successive 1s to the part will exit the part from the mode and return all
register contents to their power-on/reset status. Note, if the part is placed in one of its test modes, it may not be possible to read back
the contents of the Test Register depending on the test mode which the part has been placed.
REV. A
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