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| 型号： | EVAL-AD7731EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7731 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | 串行 |
| 输入范围： | ±1.28 V |
| 在以下条件下的电源（标准）： | 67.5mW @ 6.4kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7731 |
| 已供物品： | 板，CD |
| 相关产品： | AD7731BNZ-ND - IC ADC 24BIT SIGMA-DELTA 24DIP AD7731BRUZ-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRUZ-REEL-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRUZ-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRZ-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRZ-REEL-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRZ-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC AD7731BRU-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BRU-ND - IC ADC 24BIT SIGMA-DELTA 24TSSOP AD7731BR-REEL7-ND - IC ADC 24BIT SIGMA-DELTA 24-SOIC 更多... |
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AD7731
–13–
REV. 0
Communications Register (RS2-RS0 = 0, 0, 0)
The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the
Communications Register. The data written to the Communications Register determines whether the next operation is a read or
write operation, the type of read operation and to which register this operation takes place. For single-shot read or write operations,
once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write op-
eration to the Communications Register. This is the default state of the interface, and on power-up or after a
RESET, the AD7731 is
in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a
write operation of at least 32 serial clock cycles with DIN high, returns the AD7731 to this default state by resetting the part. Table
VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits
are in the Communications Register. CR7 denotes the first bit of the data stream.
Table VI. Communications Register
7
R
C
6
R
C5
R
C4
R
C3
R
C2
R
C1
R
C0
R
C
N
E
W
O
R
E
Z1
W
R0
W
RO
R
E
Z2
S
R1
S
R0
S
R
Bit
Location
Mnemonic
Description
CR7
WEN
Write Enable Bit. A 0 must be written to this bit so the write operation to the Communica-
tions Register actually takes place. If a 1 is written to this bit, the part will not clock on to
subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit.
Once a 0 is written to the
WEN bit, the next seven bits will be loaded to the Communica-
tions Register.
CR6
ZERO
A zero must be written to this bit to ensure correct operation of the AD7731.
CR5, CR4
RW1, RW0
Read Write Mode Bits. These two bits determine the nature of the subsequent read/write
operation. Table VII outlines the four options.
Table VII. Read/Write Mode
RW1
RW0
Read/Write Mode
0
Single Write to Specified Register
0
1
Single Read of Specified Register
1
0
Start Continuous Read of Specified Register
1
Stop Continuous Read Mode
With 0, 0 written to these two bits, the next operation is a write operation to the register
specified by bits RS2, RS1, RS0. Once the subsequent write operation to the specified regis-
ter has been completed, the part returns to where it is expecting a write operation to the
Communications Register.
With 0, 1 written to these two bits, the next operation is a read operation of the register specified
by bits RS2, RS1, RS0. Once the subsequent read operation to the specified register has been
completed, the part returns to where it is expecting a write operation to the Communications
Register.
Writing 1, 0 to these bits, sets the part into a mode of continuous reads from the register
specified by bits RS2, RS1, RS0. The most likely registers which the user will want to use this
function with are the Data Register and the Status Register. Subsequent operations to the
part will consist of read operations to the specified register without any intermediate writes to
the Communications Register. This means that once the next read operation to the specified
register has taken place, the part will be in a mode where it is expecting another read from
that specified register. The part will remain in this continuous read mode until 30 Hex has
been written to bits RW1 and RW0.
When 1, 1 is written to these bits (and 0 written to bits CR3 through CR0), the continuous
read mode is stopped and the part returns to where it is expecting a write operation to the
Communications Register. Note, the part continues to look at the DIN line on each SCLK
edge during the continuous read mode so that it can determine when to stop the continuous
read mode. Therefore, the user must be careful not to inadvertently exit the continuous read
mode or reset the part by writing a series of 1s to the part. The easiest way to avoid this is to
place a logic 0 on the DIN line while the part is in continuous read mode.
REV. A
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