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参数资料
型号： EVAL-ADAU1442EBZ
厂商： Analog Devices Inc
文件页数： 18/93页
文件大小： 0K
描述： BOARD EVAL FOR ADAU1442
标准包装： 1
系列： SigmaDSP®
主要目的： 音频，音频处理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1442
主要属性： 单芯片多通道 28/56 位音频 DSP
次要属性： I²C & SPI 接口
已供物品： 电路板，线缆，说明文档，GPIO 子板，电源
ADAU1442/ADAU1445/ADAU1446
Data Sheet
Rev. D | Page 24 of 92
Table 12. Bit Descriptions of Register 0xE220
Bit Position
Description
Default
[15:5]
Reserved
[4:0]
Start pulse select
00000
00000 = internally generated normal rate (fS,NORMAL)
00001 = internally generated dual rate (fS,DUAL)
00010 = internally generated quad rate (fS,QUAD)
00011 = fS from serial input Stereo Pair 01
00100 = fS from serial input Stereo Pair 11
00101 = fS from serial input Stereo Pair 21
00110 = fS from serial input Stereo Pair 31
00111 = fS from serial input Stereo Pair 41
01000 = fS from serial input Stereo Pair 51
01001 = fS from serial input Stereo Pair 61
01010 = fS from serial input Stereo Pair 71
01011 = fS from serial input Stereo Pair 81
01100 = fS from serial input Stereo Pair 91
01101 = fS from serial input Stereo Pair 101
01110 = fS from serial input Stereo Pair 111
01111 = fS from serial output Stereo Pair 01
10000 = fS from serial output Stereo Pair 11
10001 = fS from serial output Stereo Pair 21
10010 = fS from serial output Stereo Pair 31
10011 = fS from serial output Stereo Pair 41
10100 = fS from serial output Stereo Pair 51
10101 = fS from serial output Stereo Pair 61
10110 = fS from serial output Stereo Pair 71
10111 = fS from serial output Stereo Pair 81
11000 = fS from serial output Stereo Pair 91
11001 = fS from serial output Stereo Pair 101
11010 = fS from serial output Stereo Pair 111
11011 = fS from S/PDIF receiver1
11100 = no start pulse; core is disabled
11101 = no start pulse; core is disabled
11110 = no start pulse; core is disabled
11111 = no start pulse; core is disabled
1
fS is the LRCLK of the associated stereo audio pair in the flexible audio routing matrix whose frequency is dependent on the settings of its associated serial port and the
clock pad multiplexer. The intended function of the DSP core rate select register is to allow the DSP core to be synchronized to an external LRCLK signal that is being
used by any of the serial ports or S/PDIF receiver.
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