
ADAU1442/ADAU1445/ADAU1446
Data Sheet
Rev. D | Page 60 of 92
DSP CORE
The DSP core performs calculations on audio data as specified
by the instruction codes stored in program RAM. Because
SigmaStudio generates the instructions, it is not necessary to
have a detailed knowledge of the DSP core to use the SigmaDSP,
but a brief description is provided in this section.
Architecture
The core consists of a simple 28-/56-bit multiply-accumulate
unit (MAC) with two sources: a data source and a coefficient
source. The data source can come from the data RAM, a ROM
table of commonly used constant values, or the audio inputs to
the core. The coefficient source can come from the parameter
RAM, a ROM table of commonly used constant values. The
two sources are multiplied in a 28-bit fixed-point multiplier,
and then the signal is input to the 56-bit adder; the result is
usually stored in one of three 56-bit accumulator registers.
The accumulators can be output from the core (in 28-bit
format) or can optionally be written back into the data or
parameter RAMs.
Features
The SigmaDSP core is designed specifically for audio processing
and, therefore, includes several features intended for maximizing
efficiency. These include hardware decibel conversion and audio-
specific ROM constants.
Signal Processing
provide all signal processing functions commonly used in stereo
or multichannel playback systems. The signal processing flow is
designed using SigmaStudio software from Analog Devices. This
software allows graphical entry and real-time control of all signal
processing functions.
Many of the signal processing functions are coded using full,
56-bit, double-precision arithmetic. The serial port input and
output word lengths are 24 bits, but four extra headroom bits
are used in the processor to allow internal gains of up to 24 dB
without clipping. Additional gains can be achieved by initially
scaling down the input signal in the DSP signal flow.
COEFFICIENT SOURCE
(PARAMETER RAM,
ROM CONSTANTS, ...)
DATA OPERATIONS
(ACCUMULATORS (3), dB CONVERSION,
BIT OPERATORS, BIT SHIFTER, ...)
DATA SOURCE
(DATA RAM,
ROM CONSTANTS,
INPUTS, ...)
OUTPUTS
TRUNCATOR
56
28
56
07696-
052
Figure 51. Simplified Core Architecture