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| 型号： | EVAL-ADAV801EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/60页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADAV801 |
| 标准包装： | 1 |
| 主要目的： | 接口，模拟前端（AFE） |
| 已用 IC / 零件： | ADAV801 |
| 已供物品： | 板 |
| 相关产品： | ADAV801ASTZ-ND - IC CODEC AUDIO R-DVD 3.3V 64LQFP ADAV801ASTZ-REEL-ND - IC CODEC AUDIO R-DVD 3.3V 64LQFP |
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ADAV801
Rev. A | Page 42 of 60
Interrupt Status—Address 0011100 (0x1C)
Table 69. Interrupt Status Register Bit Map
7
6
5
4
3
2
1
0
SRCError
TxCSTINT
TxUBINT
TxCSBINT
RxCSDIFF
RxUBINT
RxCSBINT
RxERROR
Table 70. Interrupt Status Register Bit Descriptions
Bit Name
Description
SRCError
This bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample
rate converter error register. This bit remains high until the interrupt status register is read.
TxCSTINT
This bit is set if a write to the transmitter channel status buffer was made while transmitter channel status bits were being
copied from the transmitter CS buffer to the S/PDIF transmit buffer.
TxUBINT
This bit is set if the S/PDIF transmit buffer is empty. This bit remains high until the interrupt status register is read.
TxCSBINT
This bit is set if the transmitter channel status bit buffer has transmitted its block of channel status. This bit remains high
until the interrupt status register is read.
RxCSDIFF
This bit is set if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit remains
high until read, but does not generate an interrupt.
RxUBINT
This bit is set if the receiver user bit buffer has a new block or message. This bit remains high until the interrupt status
register is read.
RxCSBINT
This bit is set if a new block of channel status is read when RxBCONF3 = 0, or if the channel status has changed when
RxBCONF3 = 1. This bit remains high until the interrupt status register is read.
RxERROR
This bit is set if one of the AES3/S/PDIF receiver interrupts is asserted, and the host should immediately read the receiver
error register. This bit remains high until the interrupt status register is read.
Interrupt Status Mask—Address 0011101 (0x1D)
Table 71. Interrupt Status Mask Register Bit Map
7
6
5
4
3
2
1
0
SRCError Mask
TxCSTINT Mask
TxUBINT Mask
TxCSBINT Mask
Reserved
RxUBINT Mask
RxCSBINT Mask
RxError Mask
Table 72. Interrupt Status Mask Register Bit Descriptions
Bit Name
Description
SRCError Mask
Masks the SRCError bit from generating an interrupt.
0 = SRCError bit does not generate an interrupt.
1 = SRCError bit generates an interrupt.
TxCSTINT Mask
Masks the TxCSTINT bit from generating an interrupt.
0 = TxCSTINT bit does not generate an interrupt.
1 = TxCSTINT bit generates an interrupt.
TxUBINT Mask
Masks the TxUBINT bit from generating an interrupt.
0 = TxUBINT bit does not generate an interrupt.
1 = TxUBINT bit generates an interrupt.
TxCSBINT Mask
Masks the TxCSBINT bit from generating an interrupt.
0 = TxCSBINT bit does not generate an interrupt.
1 = TxCSBINT bit generates an interrupt.
RxUBINT Mask
Masks the RxUBINT bit from generating an interrupt.
0 = RxUBINT bit does not generate an interrupt.
1 = RxUBINT bit generates an interrupt.
RxCSBINT Mask
Masks the RxCSBINT bit from generating an interrupt.
0 = RxCSBINT bit does not generate an interrupt.
1 = RxCSBINT bit generates an interrupt.
RxError Mask
Masks the RxError bit from generating an interrupt.
0 = RxError bit does not generate an interrupt.
1 = RxError bit generates an interrupt.
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