参数资料
| 型号： | EVAL-ADE7759EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7759 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7759 |
| 已供物品： | 板 |
| 相关产品： | ADE7759ARSZRL-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7759ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP |
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ADE7759
Test Circuits
V DD
V DD
I
10 F
100nF
100nF
10 F
I
10 F
100nF
100nF
10 F
1k
AV DD DV DD RESET
DIN
di/dt CURRENT
SENSOR
100
1k
AV DD DV DD RESET
DIN
U1
ADE7759
U1
ADE7759
RB
33nF
1k
33nF
V1P
V1N
DOUT
SCLK
CS
TO SPI BUS
(USED ONLY FOR
CALIBRATION)
33nF
100
33nF
33nF
1k
33nF
V1P
V1N
DOUT
SCLK
CS
TO SPI BUS
(USED ONLY FOR
CALIBRATION)
110V
1k
600k
1k
10 F
33nF
33nF
100nF
V2N
V2P
REF IN/OUT
CLKOUT
CLKIN
IRQ
SAG
ZX
CF
Y1 22pF
3.58MHz
22pF
NOT CONNECTED
U3
110V
1k
600k
1k
10 F
33nF
33nF
100nF
V2N
V2P
REF IN/OUT
CLKOUT
CLKIN
IRQ
SAG
ZX
CF
Y1 22pF
3.58MHz
22pF
NOT CONNECTED
U3
CT TURN RATIO = 1800:1
CHANNEL 2 GAIN = 1
GAIN (CH1) RB
AGND DGND
TO
FREQUENCY
COUNTER
CHANNEL 1 GAIN = 4
CHANNEL 2 GAIN = 1
AGND DGND
TO
FREQUENCY
COUNTER
1
10
4
2.5
PS2501-1
PS2501-1
Test Circuit 1. Performance Curve (Integrator OFF)
ANALOG INPUTS
The ADE7759 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
and V2P/V2N are ± 0.5 V. In addition, the maximum signal
level on analog inputs for V1P/V1N and V2P/V2N are ± 0.5 V
with respect to AGND.
Each analog input channel has a PGA (Programmable Gain
Amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the gain register—see
Figure 5. Bits 0 to 2 select the gain for the PGA in Channel 1 and
the gain selection for the PGA in Channel 2 is made via Bits 5
to 7. Figure 4 shows how a gain selection for Channel 1
Test Circuit 2. Performance Curve (Integrator ON)
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the gain register—see Figure 5. As
mentioned previously the maximum differential input voltage is
0.5 V. However, by using Bits 3 and 4 in the gain register, the
maximum ADC input voltage can be set to 0.5 V, 0.25 V, or
0.125 V. This is achieved by adjusting the ADC reference—see
Reference Circuit section. Table I summarizes the maximum
differential input signal level on Channel 1 for the various ADC
range and gain selections.
Table I. Maximum Input Signal Levels for Channel 1
is made using the gain register.
Max Signal
ADC Input Range Selection
GAIN[7:0]
Channel 1
0.5 V
0.25 V
0.5 V
Gain = 1
Gain = 2
0.25 V 0.125 V
Gain = 1
V1P
GAIN (K)
SELECTION
0.125 V
0.0625 V
0.0313 V
0.0156 V
Gain = 4
Gain = 8
Gain = 16
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 1
Gain = 2
Gain = 4
Gain = 8
0.00781 V
Gain = 16
V IN
K
V IN
GAIN REGISTER *
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
V1N
+
7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
ADDR:
OFFSET ADJUST
0AH
( 50mV)
PGA 2 GAIN SELECT
PGA 1 GAIN SELECT
000 =
001 =
1
2
000 =
001 =
1
2
CH1OS[7:0]
BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION
BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT ON)
Figure 4. PGA in Channel 1
010 =
011 =
100 =
4
8
16
* REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
010 = 4
011 = 8
100 = 16
CHANNEL 1 FULL-SCALE SELECT
00 = 0.5V
01 = 0.25V
10 = 0.125V
Figure 5. Analog Gain Register
REV. A
–11 –
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