参数资料
| 型号： | EVAL-ADE7759EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7759 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7759 |
| 已供物品： | 板 |
| 相关产品： | ADE7759ARSZRL-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7759ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP |
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ADE7759
REFERENCE
1,
8,
2,
16
2.42V, 1.21V, 0.6V
4,
{GAIN[4:3]}
V1P
{GAIN[2:0]}
MULTIPLIER DIGITAL LPF
HPF
DIGITAL
INTEGRATOR *
TO WAVEFORM
SAMPLE REGISTER
V1
PGA1
ADC 1
Sinc 3
∫
TO MULTIPLIER
V1N
801HEX–7FFHEX
50Hz
CHANNEL 1 (ACTIVE POWER)
DATA RANGE AFTER
INTEGRATOR (50Hz)
APGAIN[11:0]
2E72Eh
+94.5% FS
V1
0.5V, 0.25V,
0.125V, 62.5mV,
31.3mV, 15.6mV,
40000h
+FS
CHANNEL 1 (ACTIVE POWER)
1EF74h
F7BAh
00000h
+63% FS
+31.5% FS
0V
2851Fh
+63% FS
3C7AEh
DATA RANGE
+94.5% FS
F0846h
E108Ch
– 31.5% FS
– 63% FS
ANALOG
00000h
2851Fh
1428Fh
+63% FS
+31.5% FS
D18D2h
000h 7FFh
801h
– 94.5% FS
INPUT
RANGE
D7AE1h
– 63% FS
00000h
EBD71h
– 31.5% FS
60Hz
APGAIN[11:0]
C0000h
ADC OUTPUT
WORD RANGE
– FS
D7AE1h
C3852h
000h
7FFh
801h
– 63% FS
– 94.5% FS
CHANNEL 1 (ACTIVE POWER)
DATA RANGE AFTER
INTEGRATOR (60Hz)
APGAIN[11:0]
* WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA VARIES DEPENDING
ON THE SIGNAL FREQUENCY BECAUSE OF –20dB/DECADE FREQUENCY RESPONSE.
26B50h
19CE0h
0CE70h
00000h
F3190h
E6320h
+94.5% FS
+63% FS
+31.5% FS
– 31.5% FS
– 63% FS
D94B0h
000h 7FFh 801h
– 94.5% FS
APGAIN[11:0]
Figure 23. ADC and Signal Processing in Channel 1
Channel 1 ADC Gain Adjust
The ADC gain in Channel 1 can be adjusted by using the multi-
plier and active power gain register (APGAIN[11:0]). The gain of
the ADC is adjusted by writing a twos complement 12-bit word
to the active power gain register. Below is the expression that
shows how the gain adjustment is related to the contents of the
active power gain register.
wave form samples are transferred from the ADE7759 one byte
(eight bits) at a time, with the most significant byte shifted out
first. The 20-bit dataword is right justified and sign extended to
24 bits (three bytes)—see Serial Interface section.
SAMPLING RATE (27.9kSPS, 14kSPS, 7kSPS, OR 3.5kSPS)
IRQ
Code = ? ADC × ? 1 +
? ?
? ?
? ?
? ?
APGAIN ? ?
2 12
SCLK
DIN
16 s
READ FROM WAVEFORM
0 0 0 01 HEX
For example, when 7FFh is written to the active power gain
register, the ADC output is scaled up by 50%. 7FFh = 2047
decimal, 2047/2 12 = 0.5. Similarly, 801h = 2047 decimal
(signed twos complement) and ADC output is scaled by –50%.
These two examples are illustrated in Figure 23.
DOUT
SIGN
CHANNEL 1 DATA
– 20 BITS
Figure 24. Waveform Sampling Channel 1
Channel 1 Sampling
The waveform samples may also be routed to the waveform
register (MODE[14:13] = 1, 0) to be read by the system master
(MCU). In waveform sampling mode, the WSMP bit (Bit 3) in
the interrupt enable register must also be set to Logic 1. The
active power and energy calculation will remain uninterrupted
during waveform sampling.
CHANNEL 1 AND CHANNEL 2 WAVEFORM SAMPLING
MODE
In Channel 1 and Channel 2 waveform sampling mode
(MODE[14:13] = 01), the output is a 40-bit waveform sample
data that contains the waveform samples from both Channel 1
and Channel 2 ADCs. Figure 25 shows the format of the 40-bit
waveform output.
When in waveform sample mode, one of four output sample
rates may be chosen by using Bits 11 and 12 of the mode regis-
ter DTRT(1, 0). The output sample rate may be 27.9 kSPS,
1 BYTE
BIT 39
CH2[19:16] CH1[19:16]
2 BYTES
CH1[15:0]
2 BYTES
CH2[15:0]
BIT 0
14 kSPS, 7 kSPS, or 3.5 kSPS—see Mode Register section. The
interrupt request output IRQ signals a new sample availability
by going active low. The timing is shown in Figure 24. The 20-bit
–18 –
Figure 25. 40-Bit Combined Channel 1 and Channel 2
Waveform Sample Data Format
REV. A
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