参数资料
| 型号： | EVAL-ADE7759EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/36页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7759 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7759 |
| 已供物品： | 板 |
| 相关产品： | ADE7759ARSZRL-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7759ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP |
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ADE7759
Mode Register (06H)
The ADE7759 functionality is configured by writing to the mode register—see Figure 45. Table VI summarizes the functionality of
each bit in the mode register.
Table VI. Mode Register
Bit
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
12, 11
Mnemonic
DISHPF
DISLPF2
DISCF
DISSAG
ASUSPEND
TEMPSEL
SWRST
CYCMODE
DISCH1
DISCH2
SWAP
DTRT1, 0
Description
The HFP (high-pass filter) in Channel 1 is disabled when this bit is set.
The LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
The frequency output CF is disabled when this bit is set.
The line voltage sag detection is disabled when this bit is set.
By setting this bit to Logic 1, both ADE7759s’ A/D converters can be turned off. In normal
operation, this bit should be left at Logic 0. All digital functionality can be stopped by suspending
the clock signal at CLKIN pin.
The temperature conversion starts when this bit is set to 1. This bit is automatically reset to
0 when the temperature conversion is finished.
Software Chip Reset. A data transfer should not take place to the ADE7759 for at least 18 μ s after
a software reset.
Setting this bit to Logic 1 places the chip in line cycle energy accumulation mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the
analog inputs V1P and V1N are connected to ADC 2.
These bits are used to select the waveform register update rate.
DTRT1
0
0
1
1
DTRT0
0
1
0
1
Update Rate
27.9 kSPS (CLKIN/128)
14 kSPS (CLKIN/256)
7 kSPS (CLKIN/512)
3.5 kSPS (CLKIN/1024)
14, 13
WAVSEL1, 0
These bits are used to select the source of the sampled data for the waveform register.
WAVSEL1, 0
Length
Source
0
0
1
1
0
1
0
1
24 bits
40 bits
24 bits
24 bits
Active Power Signal (output of LPF2)
Channel 1 and Channel 2
Channel 1
Channel 2
15
REV. A
TEST1
Writing a Logic 1 to this bit position places the ADE7759 in test mode. This is intended for fac-
tory testing only and should be left at 0.
–31 –
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