参数资料
型号: EVAL-ADUC831QSZ
厂商: Analog Devices Inc
文件页数: 13/76页
文件大小: 0K
描述: KIT DEV FOR ADUC831 QUICK START
产品培训模块: Process Control
标准包装: 1
系列: QuickStart™ 套件
类型: MCU
适用于相关产品: ADuC831
所含物品: 评估板、电源、缆线、软件和说明文档
产品目录页面: 739 (CN2011-ZH PDF)
相关产品: ADUC831BCPZ-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP
ADUC831BCPZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP
ADUC831BSZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 52MQFP
ADUC831BSZ-ND - IC ADC/DAC 12BIT W/MCU 52-MQFP
其它名称: EVAL-ADUC831QS
EVAL-ADUC831QS-ND
REV. 0
–20–
ADuC831
Table IV. ADCCON2 SFR Bit Designations
Bit
Name
Description
ADCCON2.7 ADCI
The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at
the end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Inter-
rupt Service Routine. Otherwise, the ADCI bit should be cleared by user code.
ADCCON2.6 DMA
The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode opera-
tion. A more detailed description of this mode is given in the ADC DMA Mode section. The DMA bit is
automatically set to “0” at the end of a DMA cycle. Setting this bit causes the ALE output to cease, it will
start again when DMA is started and will operate correctly after DMA is complete.
ADCCON2.5 CCONV
The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of
conversion. In this mode, the ADC starts converting based on the timing and channel configuration
already set up in the ADCCON SFRs; the ADC automatically starts another conversion once a previ-
ous conversion has completed.
ADCCON2.4 SCONV
The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is
automatically reset to “0” on completion of the single conversion cycle.
ADCCON2.3 CS3
The channel selection bits (CS3-0) allow the user to program the ADC channel selection under
ADCCON2.2 CS2
software control. When a conversion is initiated, the channel converted will be the one pointed to by
ADCCON2.1 CS1
these channel selection bits. In DMA mode, the channel selection is derived from the channel ID
ADCCON2.0 CS0
written to the external memory.
CS3 CS2 CS1 CS0 CH#
00000
00011
00102
00113
01004
01015
01106
01117
1000Temp Monitor
Requires minimum of 1 s to acquire
1001
DAC0
Only use with Internal DAC o/p buffer on
1010
DAC1
Only use with Internal DAC o/p buffer on
1011
AGND
1100
VREF
1111
DMA STOP
Place in XRAM location to finish DMA sequence,
see the ADC DMA Mode section.
All other combinations reserved
ADCCON2 – (ADC Control SFR #2)
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.
SFR Address:
D8H
SFR Power-On Default Value:
00H
Bit Addressable:
YES
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