参数资料
型号: EVAL-ADUC831QSZ
厂商: Analog Devices Inc
文件页数: 28/76页
文件大小: 0K
描述: KIT DEV FOR ADUC831 QUICK START
产品培训模块: Process Control
标准包装: 1
系列: QuickStart™ 套件
类型: MCU
适用于相关产品: ADuC831
所含物品: 评估板、电源、缆线、软件和说明文档
产品目录页面: 739 (CN2011-ZH PDF)
相关产品: ADUC831BCPZ-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP
ADUC831BCPZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP
ADUC831BSZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 52MQFP
ADUC831BSZ-ND - IC ADC/DAC 12BIT W/MCU 52-MQFP
其它名称: EVAL-ADUC831QS
EVAL-ADUC831QS-ND
REV. 0
–34–
ADuC831
SOURCE/SINK CURRENT – mA
3
05
10
15
OUTPUT
VOLTAGE
V
2
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
Figure 24. Source and Sink Current Capability with
VREF = VDD = 3 V
To reduce the effects of the saturation of the output amplifier at
values close to ground and to give reduced offset and gain errors,
the internal buffer can be bypassed. This is done by setting the
DBUF bit in the CFG831 register. This allows a full rail-to-rail
output from the DAC which should then be buffered externally
using a dual supply op-amp in order to get a rail-to-rail output.
This external buffer should be located as near as physically
possible to the DAC output pin on the PCB. Note the unbuffed
mode only works in the 0 to VREF range.
To drive significant loads with the DAC outputs, external buff-
ering may be required (even with the internal buffer enabled),
as illustrated in Figure 25. A list of recommended op-amps is in
Table VI.
ADuC831
DAC0
DAC1
Figure 25. Buffering the DAC Outputs
The DAC output buffer also features a high-impedance disable
function. In the chip’s default power-on state, both DACs are
disabled, and their outputs are in a high-impedance state (or
“three-state”) where they remain inactive until enabled in software.
This means that if a zero output is desired during power-up or
power-down transient conditions, then a pull-down resistor must
be added to each DAC output. Assuming this resistor is in place,
the DAC outputs will remain at ground potential whenever the
DAC is disabled.
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