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| 型号： | EVAL-ADUC831QSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/76页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC831 QUICK START |
| 产品培训模块： | Process Control |
| 标准包装： | 1 |
| 系列： | QuickStart™ 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC831 |
| 所含物品： | 评估板、电源、缆线、软件和说明文档 |
| 产品目录页面： | 739 (CN2011-ZH PDF) |
| 相关产品： | ADUC831BCPZ-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP ADUC831BCPZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 56LFCSP ADUC831BSZ-REEL-ND - IC MCU 62K FLASH ADC/DAC 52MQFP ADUC831BSZ-ND - IC ADC/DAC 12BIT W/MCU 52-MQFP |
| 其它名称： | EVAL-ADUC831QS EVAL-ADUC831QS-ND |
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REV. 0
–38–
ADuC831
SERIAL PERIPHERAL INTERFACE
The ADuC831 integrates a complete hardware Serial Peripheral
Interface (SPI) on-chip. SPI is an industry standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, i.e., full duplex.
It should be noted that the SPI pins are shared with the I
2C
interface pins. Therefore, the user can only enable one or the
other interface at any given time (see SPE in Table XI below).
The SPI Port can be configured for Master or Slave operation,
and typically consists of four pins, namely:
MISO (Master In, Slave Out Data I/O Pin)
The MISO (master in slave out) pin is configured as an input
line in master mode and an output line in slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as
byte wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (master out slave in) pin is configured as an output line
in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLOCK (Serial Clock I/O Pin)
The master serial clock (SCLOCK) is used to synchronize the
data being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in each
SCLOCK period. Therefore, a byte is transmitted/received
after eight SCLOCK periods. The SCLOCK pin is configured as
an output in master mode and as an input in slave mode. In master
mode the bit-rate, polarity and phase of the clock are controlled by
the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XI). In slave mode the SPICON register will have to
be configured with the phase and polarity (CPHA and CPOL) of
the expected input clock. In both master and slave modes, the data
is transmitted on one edge of the SCLOCK signal and sampled
on the other. It is important therefore, that the CPHA and CPOL
are configured the same for the master and slave devices.
Slave Select Input Pin (
SS
)
The Slave Select (
SS) input pin is shared with the ADC5 input.
In order to configure this pin as a digital input, the bit must be
cleared, e.g., CLR P1.5.
This line is active low. Data is only received or transmitted in slave
mode when the
SS pin is low, allowing the ADuC831 to be used
in single master, multislave SPI configurations. If CPHA = 1 then the
SS input may be permanently pulled low. With CPHA = 0, the SS
input must be driven low before the first bit in a byte wide transmis-
sion or reception and return high again after the last bit in that byte
wide transmission or reception. In SPI slave mode, the logic level on
the external
SS pin can be read via the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
SPICON
SPI Control Register
SFR Address
F8H
Power-On Default Value
OOH
Bit Addressable
Yes
Table XI. SPICON SFR Bit Designations
Bit
Name
Description
7
ISPI
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
6
WCOL
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5
SPE
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable the I
2C interface.
4
SPIM
SPI Master/Slave Mode Select Bit.
Set by user to enable Master Mode operation (SCLOCK is an output).
Cleared by user to enable Slave Mode operation (SCLOCK is an input).
3
CPOL
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
2
CPHA
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
1
SPR1
SPI Bit-Rate Select Bits.
0
SPR0
These bits select the SCLOCK rate (bit-rate) in Master Mode as follows:
SPR1
SPR0
Selected Bit Rate
00fOSC/2
01fOSC/4
10fOSC/8
11fOSC/16
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external
SS pin can be read via the SPR0 bit.
The CPOL and CPHA bits should both contain the same values for master and slave devices.
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| EVAL-ADUC832QS | 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk 制造商:Analog Devices 功能描述:DEVELOPMENT KIT SYSTEM |
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