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| 型号： | EVAL-ADUC834QSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 49/80页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC834 |
| 标准包装： | 1 |
| 系列： | QuickStart™ 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC834 |
| 所含物品： | 评估板，线缆，电源，软件和文档 |
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REV. A
ADuC834
–53–
TCON
Timer/Counter 0 and 1 Control Register
SFR Address
88H
Power-On Default Value
00H
Bit Addressable
Yes
Table XXVII. TCON SFR Bit Designations
Bit
Name
Description
7
TF1
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
6
TR1
Timer 1 Run Control Bit.
Set by user to turn on Timer/Counter 1.
Cleared by user to turn off Timer/Counter 1.
5
TF0
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
4
TR0
Timer 0 Run Control Bit.
Set by user to turn on Timer/Counter 0.
Cleared by user to turn off Timer/Counter 0.
3
IE1
*
External Interrupt 1 (
INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin
INT1,
depending on bit IT1 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt
was transition-activated. If level-activated, the external requesting source controls the
request flag, rather than the on-chip hardware.
2
IT1
*
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
1
IE0
*
External Interrupt 0 (
INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin
INT0, depending
on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was
transition-activated. If level-activated, the external requesting source controls the request flag,
rather than the on-chip hardware.
0
IT0
*
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
*These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
Timer/Counter 0 and 1 Data Registers
Both timer 0 and timer 1 consist of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit
register, depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte. SFR Address = 8CH, 8AH, respectively.
TH1 and TL1
Timer 1 high byte and low byte. SFR Address = 8DH, 8BH, respectively.
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| EVAL-ADUC841QSPZ | 功能描述:KIT DEV QUICK START ADUC841 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 标准包装:1 系列:PICDEM™ 类型:MCU 适用于相关产品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，线缆，元件，CD，PICkit 编程器 产品目录页面:659 (CN2011-ZH PDF) |
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