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| 型号： | EVAL-ADUC834QSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/80页 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC834 |
| 标准包装： | 1 |
| 系列： | QuickStart™ 套件 |
| 类型： | MCU |
| 适用于相关产品： | ADuC834 |
| 所含物品： | 评估板，线缆，电源，软件和文档 |
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REV. A
ADuC834
–17–
ADCSTAT
ADC Status Register. Holds general status of
the primary and auxiliary ADCs.
ADCMODE
ADC Mode Register. Controls general modes
of operation for primary and auxiliary ADCs.
ADC0CON
Primary ADC Control Register. Controls
specific configuration of primary ADC.
ADC1CON
Auxiliary ADC Control Register. Controls
specific configuration of auxiliary ADC.
SF
Sinc Filter Register. Configures the decimation
factor for the Sinc3 filter and thus the primary
and auxiliary ADC update rates.
ICON
Current Source Control Register. Allows
user control of the various on-chip current
source options.
ADC0L/M/H
Primary ADC 24-bit conversion result is held
in these three 8-bit registers.
ADC1L/H
Auxiliary ADC 16-bit conversion result is held
in these two 8-bit registers.
OF0L/M/H
Primary ADC 24-bit Offset Calibration
Coefficient is held in these three 8-bit registers.
OF1L/H
Auxiliary ADC 16-bit Offset Calibration
Coefficient is held in these two 8-bit registers.
GN0L/M/H
Primary ADC 24-bit Gain Calibration
Coefficient is held in these three 8-bit registers.
GN1L/H
Auxiliary ADC 16-bit Gain Calibration
Coefficient is held in these two 8-bit registers.
ADCSTAT—(ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions
including reference detect and conversion overflow/underflow flags.
SFR Address
D8H
Power-On Default Value
00H
Bit Addressable
Yes
Table IV. ADCSTAT SFR Bit Designations
Bit
Name
Description
7
RDY0
Ready Bit for primary ADC.
Set by hardware on completion of ADC conversion or calibration cycle.
Cleared directly by the user or indirectly by write to the mode bits to start another primary
ADC conversion or calibration. The primary ADC is inhibited from writing further results to its
data or calibration registers until the RDY0 bit is cleared.
6
RDY1
Ready Bit for auxiliary ADC. Same definition as RDY0 referred to the auxiliary ADC.
5
CAL
Calibration Status Bit.
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
4
NOXREF
No External Reference Bit (only active if primary or auxiliary ADC is active).
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below
a specified threshold. When Set, conversion results are clamped to all ones, if using external
reference.
Cleared to indicate valid VREF.
3
ERR0
Primary ADC Error Bit.
Set by hardware to indicate that the result written to the primary ADC data registers has
been clamped to all zeros or all ones. After a calibration, this bit also flags error conditions that
caused the calibration registers not to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.
2
ERR1
Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC.
1
–––
Reserved for Future Use
0
–––
Reserved for Future Use
ADC SFR INTERFACE
Both ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the
following pages.
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