参数资料
| 型号： | EX64-PTQ100I |
| 厂商： | Microsemi SoC |
| 文件页数： | 24/48页 |
| 文件大小： | 0K |
| 描述： | IC FPGA ANTIFUSE 3K 100-TQFP |
| 标准包装： | 90 |
| 系列： | EX |
| 逻辑元件/单元数： | 128 |
| 输入/输出数： | 56 |
| 门数： | 3000 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
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eX FPGA Architecture and Characteristics
1-26
Revision 10
Timing Characteristics
Timing characteristics for eX devices fall into three categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design dependency means actual delays are not
determined until after placement and routing of the user’s design are complete. Delay values may then
be determined by using the Timer utility or performing simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance
evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are
determined by net property assignment prior to placement and routing. Up to six percent of the nets in a
design may be designated as critical.
Long Tracks
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple
rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases
capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically,
no more than six percent of nets in a fully utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout
routing delays.
Timing Derating
eX devices are manufactured with a CMOS process. Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature, and worst-case processing.
Temperature and Voltage Derating Factors
Table 1-16 Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70C, VCCA = 2.3V)
VCCA
Junction Temperature (TJ)
–55
–40
0
25
70
85
125
2.3
0.79
0.80
0.87
0.88
1.00
1.04
1.13
2.5
0.74
0.81
0.83
0.93
0.97
1.06
2.7
0.69
0.70
0.76
0.78
0.88
0.91
1.00
相关PDF资料 |
PDF描述 |
|---|---|
| EX64-PTQG100I | IC FPGA ANTIFUSE 3K 100-TQFP |
| EP4CE10E22C9L | IC CYCLONE IV FPGA 10K 144EQFP |
| EP4CE10E22C8 | IC CYCLONE IV FPGA 10K 144EQFP |
| BR25S128FVT-WE2 | IC EEPROM SPI 128KB 20MHZ 8TSSOP |
| AGL060V2-QNG132I | IC FPGA 1KB FLASH 60K 132-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EX64-PTQ100PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
| EX64-PTQ128 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
| EX64-PTQ128I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
| EX64-PTQ128PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
| EX64-PTQ180 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
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