参数资料
| 型号： | EX64-PTQ100I |
| 厂商： | Microsemi SoC |
| 文件页数： | 44/48页 |
| 文件大小： | 0K |
| 描述： | IC FPGA ANTIFUSE 3K 100-TQFP |
| 标准包装： | 90 |
| 系列： | EX |
| 逻辑元件/单元数： | 128 |
| 输入/输出数： | 56 |
| 门数： | 3000 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
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Revision 10
1-1
1 – eX FPGA Architecture and Characteristics
General Description
The eX family of FPGAs is a low-cost solution for low-power, high-performance designs. The inherent
low power attributes of the antifuse technology, coupled with an additional low static power mode, make
these devices ideal for power-sensitive applications. Fabricated with an advanced 0.22 mm CMOS
antifuse technology, these devices achieve high performance with no power penalty.
eX Family Architecture
Microsemi eX family is implemented on a high-voltage twin-well CMOS process using 0.22 m design
rules. The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is
covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.
Interconnection among these logic modules is achieved using Microsemi patented metal-to-metal
programmable antifuse interconnect elements. The antifuse interconnect is made up of a combination of
amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25
with
a capacitance of 1.0fF for low-signal impedance. The antifuses are normally open circuit and, when
programmed, form a permanent low-impedance connection. The eX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines) control signals (Figure 1-1). The R-cell registers feature programmable clock
polarity selectable on a register-by-register basis. This provides additional flexibility while allowing
mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from
either the hard-wired clock or the routed clock.
The C-cell implements a range of combinatorial functions up to five inputs (Figure 1-2 on page 1-2).
Inclusion of the DB input and its associated inverter function enables the implementation of more than
4,000 combinatorial functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-flop to imitate an R-cell via the use of the CC
macro. This is particularly useful when implementing non-timing-critical paths and when the design
engineer is running out of R-cells. More information about the CC macro can be found in the Maximizing
Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros application note.
Figure 1-1 R-Cell
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLR
PSET
Y
DQ
Routed
Data Input
S0
S1
相关PDF资料 |
PDF描述 |
|---|---|
| EX64-PTQG100I | IC FPGA ANTIFUSE 3K 100-TQFP |
| EP4CE10E22C9L | IC CYCLONE IV FPGA 10K 144EQFP |
| EP4CE10E22C8 | IC CYCLONE IV FPGA 10K 144EQFP |
| BR25S128FVT-WE2 | IC EEPROM SPI 128KB 20MHZ 8TSSOP |
| AGL060V2-QNG132I | IC FPGA 1KB FLASH 60K 132-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EX64-PTQ100PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
| EX64-PTQ128 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
| EX64-PTQ128I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
| EX64-PTQ128PP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
| EX64-PTQ180 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:eX Family FPGAs |
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