参数资料
| 型号： | EX64-PTQ100I |
| 厂商： | Microsemi SoC |
| 文件页数： | 8/48页 |
| 文件大小： | 0K |
| 描述： | IC FPGA ANTIFUSE 3K 100-TQFP |
| 标准包装： | 90 |
| 系列： | EX |
| 逻辑元件/单元数： | 128 |
| 输入/输出数： | 56 |
| 门数： | 3000 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
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eX FPGA Architecture and Characteristics
1-12
Revision 10
Programming
Device programming is supported through Silicon Sculptor series of programmers. In particular, Silicon
Sculptor II is a compact, robust, single-site and multi-site device programmer for the PC.
With standalone software, Silicon Sculptor II allows concurrent programming of multiple units from the
same PC, ensuring the fastest programming times possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition, integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor II also provides extensive hardware self-testing capability.
The procedure for programming an eX device using Silicon Sculptor II is as follows:
1. Load the *.AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Microsemi offers device volume-programming services
either through distribution partners or via in-house programming from the factory.
For more details on programming eX devices, please refer to the Programming Antifuse Devices
application note and the Silicon Sculptor II User's Guide.
Probing Capabilities
eX devices provide internal probing capability that is accessed with the JTAG pins. The Silicon Explorer II
Diagnostic hardware is used to control the TDI, TCK, TMS and TDO pins to select the desired nets for
debugging. The user simply assigns the selected internal nets in the Silicon Explorer II software to the
PRA/PRB output pins for observation. Probing functionality is activated when the BST pins are in JTAG
mode and the TRST pin is driven HIGH or left floating. If the TRST pin is held LOW, the TAP controller
will remain in the Test-Logic-Reset state so no probing can be performed. The Silicon Explorer II
automatically places the device into JTAG mode, but the user must drive the TRST pin HIGH or allow the
internal pull-up resistor to pull TRST HIGH.
When you select the Reserve Probe Pin box, as shown in Figure 1-12 on page 1-10, the layout tool
reserves the PRA and PRB pins as dedicated outputs for probing. This reserve option is merely a
guideline. If the Layout tool requires that the PRA and PRB pins be user I/Os to achieve successful
layout, the tool will use these pins for user I/Os. If you assign user I/Os to the PRA and PRB pins and
select the Reserve Probe Pin option, Designer Layout will override the "Reserve Probe Pin" option and
place your user I/Os on those pins.
To allow for probing capabilities, the security fuse must not be programmed. Programming the security
fuse will disable the probe circuitry. Table 1-8 on page 1-13 summarizes the possible device
configurations for probing once the device leaves the Test-Logic-Reset JTAG state.
Silicon Explorer II Probe
Silicon Explorer II is an integrated hardware and software solution that, in conjunction with Microsemi
Designer software tools, allow users to examine any of the internal nets of the device while it is operating
in a prototype or a production system. The user can probe into an eX device via the PRA and PRB pins
without changing the placement and routing of the design and without using any additional resources.
Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the
debug cycle.
Silicon Explorer II does not require re-layout or additional MUXes to bring signals out to an external pin,
which is necessary when using programmable logic devices from other suppliers.
Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II
attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the design verification process at their desks and
reduces verification time from several hours per cycle to a few seconds.
The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS and TDO) to select the desired
nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation.
Figure 1-13 on page 1-13 illustrates the interconnection between Silicon Explorer II and the eX device to
perform in-circuit verification.
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